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I was working on pandaboard, when this problem occurred to me. pandaboard uses OMAP 4430, a harvard based architecture. The board has 1GB memory (DDR2 ram). But a harvard architecture requires two memories right ?

Here is what I understand the linux kernel image is stored in MMC/SD card and then pulled out by the bootloader into memory. Now, where is the bootloader running from (is it the 1GB ram?). Where does the bootloader dump the kernel image ?(again, is it the 1GB ram ?)

ROMANIA_engineer
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Anay
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  • http://infocenter.arm.com for this kind of question you look for the TRM, technical reference manual for the ARM core of interest. the ti omap 4430 uses a Cortex-A9 mpcore. So go down to cortex-a then the a9 then the trm for the core. In there you will find the amba axi bus (the cores external interface) described. Hmm, actually it specifies AMBA 3, which back to the arm site you can get the AMBA documents as well. Look at the ARPROT[2] bit. – old_timer Jan 20 '12 at 06:45

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ARM architecture is often called "modified Harvard". It has a single linear (4GB) memory space, but uses different buses (and caches) for code and data. This allows it to read code or execute data, just like x86.

Note that this does not hold for all ARM chips. Some of them (e.g. Cortex-M0 cores) use single bus for code and data, so they're actually von Neumann.

Igor Skochinsky
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  • same bus, same cache(s), different control signals to indicate what type of transaction. Allowing both the cache and external (to the core/l2 cache) bus interfaces to choose to handle the different transaction types as they please. I dont think I have seen an arm where the data and instructions were separate, you can have a bootloader that using data transactions writes the program to ram then have the processor execute from that ram (using instruction transactions). – old_timer Jan 20 '12 at 06:29