What does "net" stand for in Verilog?

Question

I'm just starting to learn Verilog. As I understand, Verilog has net datatypes.

What does net stand for?

score 8 · Accepted Answer · answered Apr 02 '12 at 11:25

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A net is such a data type, where you don't use it for storing values. They represent physical connections. You can think of wire as a net data type.
You can see more on nets here.

answered Apr 02 '12 at 11:25

sgowd

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A `wire` is not a _datatype_,; it is one of a few categories of nets.Net's represent connections as opposed to variables which hold values. – dave_59 Nov 08 '20 at 17:24

dave_59 · Answer 2 · 2020-11-08T17:24:31.313

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A net is short for network, and a network is a group of devices that share a common connection, a wire in most cases here. Net's represent connections as opposed to variables which hold values. I wrote a short article to explain why Verilog has nets.

edited Nov 08 '20 at 17:24

answered Sep 14 '13 at 16:03

dave_59

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score 1 · Answer 3 · answered Jun 16 '15 at 06:09

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Nets : represent structural connections between components.Nets have values continuously driven on them by the outputs of the devices to which they are connected to. i.e. nets get the output value of their drivers. If a net has no driver, it gets the value of z(high impedance).

answered Jun 16 '15 at 06:09

prasad pattadakal

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Could you please elaborate more your answer adding a little more description about the solution you provide? – abarisone Jun 16 '15 at 06:35

score 1 · Answer 4 · answered Jul 16 '16 at 06:59

IEEE 1364-2005

4.2 Nets and variables:

There are two main groups of data types: the variable data types and the net data types. These two groups differ in the way that they are assigned and hold values. They also represent different hardware structures.

4.2.1 Net declarations:

The net data types can represent physical connections between structural entities, such as gates. A net shall not store a value (except for the trireg net). Instead, its value shall be determined by the values of its drivers, such as a continuous assignment or a gate.

and the syntax table that follows says:

net_type ::= supply0 | supply1 | tri | triand | trior | tri0 | tri1 | uwire | wire | wand | wor

Interpretation

A net is a set of data types, one of which is wire.

Those data-types have in common that unlike registers they don't have memory: they are just intermediate results determined by their input. Much like the intuitive notion of wires.

What does "net" stand for in Verilog?

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