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Questions tagged [apic]

The APIC units are responsible for delivering interrupts from interrupt sources to interrupt destinations throughout the multiprocessor system.

The Advanced Programmable Interrupt Controller (APIC) is based on a distributed architecture in which interrupt control functions are distributed between two basic functional units, the local unit and the I/O unit. The local and I/O units communicate through a bus called the Interrupt Controller Communications (ICC) bus. The local APIC units also provide interprocessor interrupts (IPIs), which allow any processor to interrupt any other processor or set of processors.

More at Intel MultiProcessor Specification - http://www.intel.com/design/pentium/datashts/24201606.pdf

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About Linux NMI watchdog

Now I encounter a problem about Linux NMI Watchdog. I want to use Linux NMI watchdog to detect and recovery OS hang. So, I add "nmi_watchdog=1" into grub.cfg. And then check the /proc/interrupt, NMI were triggered per second. But after I load a…
silverbullettt
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How CPU finds ISR and distinguishes between devices

I should first share all what I know - and that is complete chaos. There are several different questions on the topic, so please don't get irritated :). 1) To find an ISR, CPU is provided with a interrupt number. In x86 machines (286/386 and above)…
ultimate cause
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x86 PIC, is it correct for QEMU to raise interrupts on all CPUs?

I recently had to work around a proprietary OS issue with the x86 PIC where the OS expected timer interrupts ONLY on CPU0. I enabled the IO-APIC to get around this and did CPU steering so the interrupts went only to CPU0. Problem solved. I was told…
Goblinhack
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Intel Local APIC Spurious Interrupt

I'm developing now a code snippet that should enable\disable local APIC. I've seen in the Intel manual that I have to set a spurious interrupt vector prior to enabling LoAPIC. In the Intel Manual I see the following explanation: A special…
RRR
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Help with APIC functions in Linux

I'm trying to play around with the local APIC functions in the 2.6.32.40 linux kernel, but I am having some issues. I want to try to send a Non-Maskable Interrupts (NMI) to all of the processors on my system (I am using a Intel i7 Q740). First I…
John
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Linux core ids are missing in cpu info

I've a issue with am machine I'm running some paralell calculations on. Until now I assumed that core ids need to be sequentially. But on this machine I have: lscpu I get the following Output for: /bin/cat /proc/cpuinfo | grep 'core id' Since…
HolgerBarlt
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Change embedded image type in APIC ID3 tag via Mutagen

I have a large music library which I have just spent around 30 hours organizing. For some of the MP3 files, I embedded the cover art image as type 0 (Other) and I'd like to change it to type 3 (Front Cover). Is there a way to do this in Python,…
Naftuli Kay
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Why can't I handle NMI?

I want to handle NMI and do something when NMI occur. Firstly I write a naive nmi handler: static irqreturn_t nmi_handler(int irq, void* dev_id) { printk("-#_#- I'm TT, I am handling NMI.\n"); return IRQ_HANDLED; } And write a module to…
silverbullettt
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Documentation on MSI Address/Data register content expectations for AMD cpus?

Where I can find info on AMD Ryzen CPUs and how they expect MSI address/data to be programmed? The Intel manual is crystal clear in its description (pictured below) but MSI Address/Data registers are implementation dependent according to the PCIe…
Omar Darwish
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How does MSI-X triggers interrupt handlers? Is there a need to poll the chosen memory address?

I have a small kernel which is booted with UEFI. I'm using QEMU for virtualization. I want to write a xHCI driver to support USB keyboards in my kernel. I'm having trouble to find concise and clear information. I "found" the xHCI in my kernel. I…
user123
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Accessing another processor's local APIC

The documentation for the Intel 64 and IA-32 says that the local APIC's register space can be remapped to other physical address. My question is, is it possible to access other processor's local APIC register space when they are mapped to different…
K. Mihaylov
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APIC multi-core startup Protocol and ICR starting up address

I am writing a boot load and try to test Inter-Processor Interrupt. I got the following 2 questions blocked me: 1, Where I can find the procedure of starting up APs; 2, When issuing IPI, where I should load the memory address to tell the target…
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Understanding the virtual APIC page for x2APIC

I am writing a VMM, and I'm trying to support virtual accesses to the x2APIC's registers by a guest OS running in VMX non-root mode. I want to start off by doing something simple, such as reading the local APIC ID from within the guest OS. I've…
Jack Humphries
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how to avoid caching when writing to mmio registers?

I'm writing a custom os in virtualbox and having trouble writing and reading successfully from the IOAPIC mmio registers. i.e. It seems to ignore the index register write. After loading R8 with the IOAPIC base address (determined from ACPI…
poby
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Implement Message Signaled Interrupt in DOS mode

I'm bit stuck at programming device MSI(Message Signaled interrupt) and any pointers welcomed...(my environment is Watcom C + DOS/32a - dos extender, in flat mode...) @ PIC(8259) mode is ok for me... I list what I have done as below and maybe…
liaoo
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