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Questions tagged [intel-tsx]

Intel's Transactional Synchronization Extension is transactional memory, allowing lock-free atomic transactions that read and write multiple memory locations.

Don't use for this - it has been repurposed for some JavaScript React thing.
Wrong usage of the [tsx] tag on Meta.

TSX is Intel's Transactional Synchronization Extension for transactional memory, including HLE (Hardware Lock Elision) and RTM (Restricted Transactional Memory)

It provides additional x86 assembly instructions and instruction prefixes for activating/deactivating a transactional access to memory and avoid hardware locking if possible.

The feature has been repeatedly disabled via Microcode update after different attempts to implement it in different CPU families due to correctness and security issues.

As of June 2020, HLE ended up being deprecated in latest Intel® 64 and IA-32 Architectures Software Developer’s Manual (see 2.5 Intel instruction set architecture and features removed). RTM is still not deprecated and possibly can be used in some current or future CPUs.

More information:

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Will runtimes like CLR and JVM be able to use Haswell TSX instructions?

After reading Anandtech on 'Haswell TSX' (tranactional memory barriers) I immediately wondered if CLR/JVM will be able to make use of these in C#/Java/Scala/F# for heavily parallel applications (C# Rx/TPL/TFD).
yzorg
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How to use Intel TSX with C++ memory model?

I think C++ does not cover any sort of transaction memory yet, but still TSX can somehow fit using "as if rule" into something that is governed by C++ memory model. So, what happens on successful HLE operation, or successful RTM transaction? Saying…
Alex Guteniev
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Has Hardware Lock Elision gone forever due to Spectre Mitigation?

Is this correct that Hardware Lock Elision is disabled for all current CPUs due to Spectre mitigation, and any attempt to have a mutex using HLE intrinsics/instructions would result in usual mutex? Is this likely that there will not be anything like…
Alex Guteniev
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Enable/Disable Hardware Lock Elision

I am using glibc 2.24 version. It has lock elision path included for pthread_mutex_lock implementation with Transactional Synchronization Extensions such as _xbegin() and _xend(). The hardware is supposed to support lock elision as hle CPU flag is…
Ana Khorguani
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Is Intel® Transactional Synchronization Extensions New Instruction (TSX-NI) difference from Intel TSX?

I found on Intel's page https://ark.intel.com/products/97123/Intel-Core-i5-7500-Processor-6M-Cache-up-to-3_80-GHz that this processor support TSX-NI technology but I can't find any information about it on google. Is it the same as Intel TSX. If…
Phạm Văn Thông
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mysterious rtm abort using haswell tsx

I'm experimenting with the tsx extensions in haswell, by adapting an existing medium-sized (1000's of lines) codebase to using GCC transactional memory extensions (which indirectly are using haswell tsx in this machine) instead of coarse grained…
orm
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Understanding ARM Transactional Memory Extensions

The ARM Transactional Memory Extensions have a fairly straightforward description of how one would use them: sem_post: TSTART X0 // Start of outer transaction CBNZ test_fail // No reason for this routine to cancel or fail LDR …
squirem
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What is the status of the TSX-related Skylake errata SKL-105?

As is well known, Intel had to disable TSX in the Haswell-series of processors via a microcode updates. This was due to a bug in the TSX implementation that could give erroneous results if these instructions were used. What seems to be less well…
Morty
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hardware transactional memory: _xbegin() return 0

By gcc docs: x86-transactional-memory-intrinsics.html, when transaction failed/abort, _xbegin() should return a abort status . However, I find it return 0 sometimes. And the frequency is very high. What kind of situation that **_xbegin()**will…
Waker Leo
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Emulating Intel TSX instructions

I'd like to experiment with the new Intel TSX instructions in advance of the chip becoming available. Does Intel make an emulator available, or is there some other technique that is widely used?
James L
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Are Intel TSX prefixes executed (safely) on AMD as NOP?

I have MASM synchronizing code for an application which runs on both Intel and AMD x86 machines. I'd like to enhance it using the Intel TSX prefixes, specifically XACQUIRE and XRELEASE. If I modify my code correctly for Intel, what will happen when…
Ira Baxter
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Is it possible to debug Intel TSX?

I would like to utilize Intel TSX to program lock-free code. xbegin my_inst1 my_inst2 xend However, because of some reasons, one of my instructions inside TSX execution TSX abort. I would like to know which instruction generates the fault and make…
ruach
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How to check for TSX support?

My current attempt: /**simplified from * https://software.intel.com/en-us/articles/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family **/ #include #include #if defined(_MSC_VER) # …
User1291
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TSX: Get the address that caused the abort

From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever. But when a…
William Leiserson
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Assembler xbegin raise Illegal instruction

My assembly code raises Illegal Instruction when calls xbegin. Is there any problem? Here is my code. main.c if ( rtm_begin() == 0 ) { //do something. } rtm.S rtm_begin: xbegin 1f mov $0, %rax retq 1: mov $-1, %rax …
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