4

From another question, clearly the Intel TSX read/write set is hidden. And this is understandable, especially since it allows them to screw with design and implementation and possibly try things like bloom filters or whatever.

But when a transaction aborts, it would be good to see what address - or cache line - caused it (when such a thing was the reason for the abort). Is the address exposed anywhere?

Peter Cordes
  • 328,167
  • 45
  • 605
  • 847
William Leiserson
  • 155
  • 1
  • 8
  • 1
    Skylake has perf counters for events like `hle_retired.aborted` and `rtm_retired.aborted`. Those are "precise" events, so possibly you could see which instruction is causing aborts (but not the actual address). There are several other perf counters for other TSX events, like different abort causes, as well as `rtm_retired.commit` and `.start`. I haven't used TSX myself, so IDK how useful that ends up being when trying to tune something to reduce aborts, but I think that's what Intel thinks you should do. Intel's optimization manual has a whole chapter on TSX, too. – Peter Cordes Oct 10 '17 at 21:37
  • Thanks Peter. Yeah, in some cases I know _why_ the transaction aborted, and I can do something to make it succeed in subsequent attempts -- but only if I know which cache line caused the abort. I'll take a look at the optimization manual. – William Leiserson Oct 12 '17 at 00:16

1 Answers1

2

After talking to folks at Intel, there is no way to do this [citation]. The address is not preserved through an abort. There are clever hacks to get, e.g., the address of the instruction that was executed (see citation), but not the address of the write.

William Leiserson
  • 155
  • 1
  • 8