Haswell Transactional Memory read-set and write-set information

Question

Recently, Intel release haswell machines which support hardware transactional memory called transactional synchronization extension(TSX).

As Intel manual said, Speculative memory operations, write-set and read-set, are buffered in L1 cache and L2 cache each. (not exactly)

Then, Can I track transactional memory operations and get information like address, and values of read/write-set?

score 1 · Answer 1 · answered May 06 '15 at 11:10

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You cannot. There is no (public) interface to the HTM hardware buffers.

answered May 06 '15 at 11:10

Matthew G.

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Skylake has perf counters for events like `hle_retired.aborted` and `rtm_retired.aborted`. Those are "precise" events, so possibly you could see which instruction is causing aborts. – Peter Cordes Oct 10 '17 at 21:34

score 0 · Answer 2 · answered Jun 05 '17 at 08:28

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Read-Set and Write-Set are in CPU Cache, there is no address to access, You can't track, but you can clean the cache by code. For Example, you can give assignments to the array.

answered Jun 05 '17 at 08:28

egraldlo

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Haswell Transactional Memory read-set and write-set information

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