short for: simple MIPS
MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.).
SMIPS is the version of the MIPS instruction set architecture (ISA). It stands for Simple MIPS since it is actually a subset of the full MIPS ISA. The MIPS architecture was one of the rst commercial RISC (reduced instruction set computer) processors, and grew out of the earlier MIPS research project at Stanford University.
MIPS stood for Microprocessor without Interlocking Pipeline Stages and the goal was to simplify the machine pipeline by requiring the compiler to schedule around pipeline hazards including a branch delay slot and a load delay slot. Today, MIPS CPUs are used in a wide range of devices:
- Casio builds handheld PDAs using MIPS CPUs
- Sony uses two MIPS CPUs in the Playstation-2
- Many Cisco internet routers contain MIPS CPUs
- Silicon Graphics makes Origin supercomputers containing up to 512 MIPS processors sharing a common memory
MIPS implementations probably span the widest range for any commercial ISA, from simple single-issue in-order pipelines to quad-issue out-of-order superscalar processors.
SMIPS processor specification found here.
