Questions tagged [vliw]

VLIW (Very Long Instruction Word) - processor arcitecture designed to exploit instruction level parallelism (ILP).

Processors based on VLIW architecture can execute many instructions in the same time. Theese instructions are located into long instruction words. In contrast with superscaler architectures, VLIW requires instructions to be staticly put in long words. That makes the CPU more simple, but all the work on determining the instruction parallelism is put on the compiler. That makes a good optimizing compiler nessesary for good performance and the compiler construction becomes very complex.

First implementations of VLIW processors were made in late 1980s by the company Cydrome but it failed. In 1990s HP also researched VLIW-based processors.

In 1989 Intel introduced i860 - the first 64 bit and the first VLIW CPU. This chip did not archive commercial success and the project was closed in 1990. In 2001 Intel and HP intrduced Itanium processor based on IA-64 architecture. It was based on modified VLIW architecture called EPIC.

In 2000 Transmeta introduced the Crusoe CPU based on VLIW. Its notable feature was executing x86 instructions by using some sort ov virtual machine.

In 2007 MCST introdused the processor Elbrus that has its own VLIW based architecture. Working on this model line MCST later developed the processors Elbrus-2S+, Elbrus-4S and announced the 8-core VLIW processor Elbrus-8S. Theese processors also can execute x86 instructions using binary translation.

Beside general-purpose processors VLIW also had some usage in GPU systems. For example the AMD Radeon HD 2900 XT GPU had shader processor based on VLIW.

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LLVM compiler infrastructure for VLIW architectures

Do you know how strong VLIW architectures (or EPIC, like Itanium) support exists in LLVM compiler infrastructure? Are there good documents/slides materials on this?
osgx
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superscalar and VLIW

I want to ask some questions related to ILP. A superscalar processor is sort of a mixture of the scalar and vector processor. So can I say that architectures of vector processor follows super-scalar ? Processing multiple instructions concurrently…
anasanjaria
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GCC compiler infrastructure for VLIW architectures

Do you know how strong VLIW architectures support exists in GCC compiler infrastructure? I know that there are some VLIW architectures supported by GCC. Looking at them, it seems that the pipeline optimizations are left to another optimization…
Serge C
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What's the advantage of compiler instruction scheduling compared to dynamic scheduling?

Nowadays, super-scalar RISC cpus usually support out-of-order execution, with branch prediction and speculative execution. They schedule work dynamically. What's the advantage of compiler instruction scheduling, compared to an out-of-order CPU's…
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very long instruction that consists of operations with different latencies

Consider a VLIW processor with an issue width equal to N: this means that it is able to start N operations simultaneously, so each very long instruction can consist of a maximum of N operations. Suppose that the VLIW processor load a very long…
enzom83
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Are SIMD and VLIW instructions the same thing?

What exactly is the difference between SIMD (Single Instruction Multiple Data) and VLIW (Very Long Instruction Word)? Is one a subset of the other? Or are they two completely difference things?
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Why are name dependencies (WaR, WaW) in ILP architectures problematic?

Assume the following two instructions are executed simultaneously: addi $t0, $t1, 4 addi $t1, $t2, 4 It's an anti-dependence, or Write-after-Read. Assuming they are executed at the same time, wouldn't the first instruction still read the correct…
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VLIW - Instructon width performance increase

Would doubling the amount of instructions in a VLIW allow for a processor to achieve double the performance since it can execute twice as many operations in parallel?
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Power efficient and Speed efficient architecture for Multimedia Applications

I am working on evaluating a embedded processor architecture which offers below features: 8 SIMD co-processing DSP kind of cores, Each core can do a 8 way SIMD Each core is a 8 execution slot VLIW as well. I want to use high video encoder(H.264,…
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How ALU execute instruction in AMD GPU (VLIW)?

I wanna ask something about OpenCL programming. I understand that a quarter of wavefront can issue instruction for each cycle clock and it will need four cycle clock to call a wavefront. To finish the instruction in VLIW architecture, it will need…
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Instruction Level Parallelism (ILP) Methods

I'm trying to learn about the methods used in instruction level parallelism and the differences between them. My question here is, given an instruction set that was initially made to run at a processor without instruction level parallelism, which…
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Reorder Buffer in Speculative Execution always needed?

I understand the need for re-order buffer in speculative execution. However, given a sequence of non-speculative instructions without any branches, why is it that all these instructions still have to go through the ROB and then commit in order? …
appusajeev
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Opencl and HD5850

I dont have an HD5850 but how can I know maximum workgroup size of it for opencl ? What is the preferred floating point vector width for HD5850? I suspected it was 5 but did not work on a friends computer who has 5850. Tried width 4 but did not work…
huseyin tugrul buyukisik
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