Sum of Array elements VHDL

Question

I am new to VHDL and I searched all of the internet and i didnt find anything that would help me !

I am trying to add the elements of an array (32 Elements !), so i cant just write for example s <= s(0) + s(1) + s(3) ... s(5) + ....s(32)

how can i generalise such a calculation ?? or what am i doing wrong ?

My Code (that didnt work in the simulation) is .. (just for 5 elemets ....)

library IEEE;
library work;
library std;

use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use ieee.std_logic_arith.all;

entity main is Port (
    EIN   : in std_logic;
    AUS_1 : out std_logic_vector(3 downto 0));
end main;

architecture Behaviour of main is

    type Cosinus is array (0 to 4) of std_logic_vector(3 downto 0); 
    type Sinus is array (0 to 4) of std_logic_vector(3 downto 0); 

    Signal SumSin :std_logic_vector(3 downto 0);

begin

    main : process(Ein)
        variable Cos : Cosinus;   
        variable Sin : Sinus;
    begin

        if( Ein='1' )  then
            sin(0) := "0011";
            sin(1) := "0001";
            sin(2) := "1010";
            sin(3) := "1111";
            sin(4) := "1110";

            for n in 0 to 4 loop
                SumSin <= SumSin + Sin(n);               
            end loop;
        else 
            sin(0) := "1011";
            sin(1) := "0101";
            sin(2) := "1000";
            sin(3) := "1001";
            sin(4) := "1100";

            for n in 0 to 4 loop
                SumSin <= SumSin + Sin(n);                         
            end loop;
        end if;
    end process;

    Aus_1 <= SumSin;    
end Behaviour;

I would be thanksfull

There are a lot of problems with this program but I think the biggest one is a misunderstanding of signal assignment. See this post for an explanation of how signal assignment works. http://stackoverflow.com/questions/13954193/is-process-in-vhdl-reentrant As to what to do about it : one solution would be to make SumSin a variable, and copy it (via a single signal assignment) to Aus at the end of the process. — , Dec 27 '12 at 23:17

score 2 · Answer 1 · answered Jan 08 '13 at 14:52

First... Don't use std_logic_arith.

Then, Use a variable for the running sum and assign is to a signal afterwards:

 ...
 main : process(Ein)
     variable Cos : Cosinus;   
     variable Sin : Sinus;
     variable SumSin : signed(3 downto 0);
 begin
     sumsin := (others => '0');
 ....
        for n in Sin'range loop
            SumSin := SumSin + Sin(n);                         
        end loop;
     end if;
     Aus_1 <= SumSin;    
  end process;

Sum of Array elements VHDL

1 Answers1