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I thought of building a synthesis tool which is based on dedicated hardware in order to accelerate the developing of an RTL.

  1. Are there any HW based platforms that synthesis RTL ?
  2. Can one approximatly estimate how fast is it in compare to Synopsis tool

The idea is to make kind of bootstrapping of vhdl/verilog/netlist synthesizer, a platform that makes a big state machine implemented in HW that sensitizing all the RTL (Writing a compiler in its own language shows the close idea for SW world).

Community
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0x90
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  • Good question... But if it was feasible, you could buy it right now from the FPGA companies, with there FPGAs on it? At least, the market need is there! – vermaete Feb 22 '13 at 10:48
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    A very good idea. Nearly all the stages can be efficiently parallelised - synthesis (at least module-level), map, place-and-route. Although it is not clear if doing so on a simple cluster won't be easier. – SK-logic Feb 22 '13 at 13:24

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As always, when the question presupposes "do it in hardware", the answer always has to be "show which bottlenecks the hardware will fix and how ". Until you understand the problem well enough to answer that question in more than a handwaving fashion, its all guesswork.

As another has noted - if it were sensible (financially), there's a big enough market of frustrated engineers waiting for synthesis to complete that it would already be there.

If it's just for a fun project, then sure, have at it :)

Martin Thompson
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    + Right. First do it in software. Then [*tune the bewillikers out of it*](http://stackoverflow.com/a/927773/23771). Then you are left with the part that takes the most time, and see if it could be done in special hardware. – Mike Dunlavey Feb 22 '13 at 14:04
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Here's a recent thesis about the topic, and the author has written a book as well. Given the cost of hardware development this probably isn't practical today.

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That's a very interesting idea, and to answer your first question I'm fairly sure there are no existing products like this commercially available.

You should know that synthesis tools are extremely complex, however. Creating what you want is going to be a lot of work, I would say that even a feasibility study (which, among other questions, should answer your second question) would be enough for a master's thesis.

Like Martin said there are tons of frustrated engineers out there with designs that take hours to synthesize (I'm one of them!). Still both Altera's and Xilinx' synthesis tools utilize the six-core processor in my computer very badly, especially if I don't do any design partitioning. This leads me to believe that parallelizing the synthesis process isn't easy, although I tend to overestimate engineers at big companies.

pc3e
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  • I'm not sure you over-estimate (all) the engineers at big companies, just the big companies care *more* about other things (so far...) – Martin Thompson Feb 23 '13 at 15:13