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I am having difficulty in understanding the use of unions and utructures in SystemVerilog. I know that they allocate memory in different ways, but I want to know in depth about structures and unions. The LRM is hard for someone like me to understand.

toolic
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chitranna
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2 Answers2

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Structures and unions in SystemVerilog are very similar to structures and unions in C. So if you are looking for use cases, it may be helpful to read up on how they can be used in C.

Here is a question that addresses this: Difference between a Structure and a Union in C

SystemVerilog adds the distinction of packed vs. unpacked for structures and unions. Packed unions must contain types that are all the same size (# of bits).

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dwikle
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The answer to your question depends a lot on whether you are trying to write synthesizable RTL code, or not. For RTL, struct and unions provide different ways of accessing bits. See How does a system verilog structure be realized in hardware? are the members declared as wires?

For testbench or other code, these types are often used when crossing the language boundary into C.

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dave_59
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