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I have seen lots of system verilog program examples representing packets of data as a packed structure. Does this data travel serially like a packet? How does a system verilog structure be realized in hardware?

user3315683
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2 Answers2

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A packed structure in SystemVerilog simply gives you an alternative way to access fields of a signal by name instead of by bit position. For example

typedef struct packed {
     logic [2:0] field1; // 3-bits
     logic [4:0] field2; // 5-bits
} signal_t; // 8-bits

You can now declare either a wire or variable with that type

wire signal_t sigA;
var signal_t sigB;

(the var keyword is implicit is most places except in a port declaration)

You can now access field1 as either sigA[7:5] or sigA.field1.

Unpacked structures, as nguthrie points out, provide a hierarchical grouping of variables, but they also provide a stronger types than Verilog. See my application note on this.

dave_59
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  • Thanks Dave, Can you further elaborate on var. If I further extend on your example and I utilized "var signal_t sigB,sigC;", how do you think "always @(posedge clk)begin sigC<=sigB; end " translate to? . Does it mean that I am clocking out sigB data in the form of a bus(of 8bits wide) to a register sigC. – user3315683 Feb 19 '14 at 08:17
  • Yes, the synthesized behavior is just the same as if you had declared it as `reg [8:0] sigC;`. But with the **struct** you have new ways of referencing the individual bits. – dave_59 Feb 19 '14 at 09:22
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Structures are just a convenient way of encapsulating variables. It is a way to show that these variables should be operated on as a group. However, calling something a packet is not going to get the synthesizer to create the hardware that you want. It is up to you to create the logic for the protocol that you are dealing with.

nguthrie
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  • I find it a little tricky to work with system verilog. In verilog the way I visualize the transfer of packets,is by loading parallel bits of data to perhaps a shift register. In order to transfer this data packet, I clock out the loaded data from the shift register serially. Can you try to correlate this logic with a system verilog structure? – user3315683 Feb 19 '14 at 08:09
  • Exactly the same but now you load part of the structure into the shift register. Something like `shift_reg <= packet.data;` – nguthrie Feb 20 '14 at 00:14