Flip flop implementation with process. [VHDL]

Question

My question is in regards to the following code:

library ieee;
use ieee.std_logic_1164.all;

entity exam is port (
    I,CLK,RESET : in std_logic;
    Q : out std_logic
);
end entity;

architecture exam_arc of exam is
    signal temp_sig : std_logic;
begin
    process (CLK,RESET)
    begin
        if RESET = '1' then
            temp_sig <='0';
        elsif CLK'event and CLK='1' then
            temp_sig <= I;
        end if;
        Q <= temp_sig;
    end process;
end exam_arc;

It seems that this piece of code simulates a D flip flop that operates on rising edge of the clock, however the answer [this question is taken from an exam] to this question claims that this D flip flop operates on falling edge of the clock.

What kind of flip flop this VHDL code simulates?

Proper code indentation prevents eye-cancer – I heard.. – drahnr Jul 15 '13 at 16:39 — drahnr, Jul 15 '13 at 16:39

score 5 · Accepted Answer · answered Jul 15 '13 at 22:36

5

It's a trick question. Note that the process wakes up on both rising and falling clock edges, and that the intermediate signal temp_sig is assigned on the rising_edge.

Put that together with the semantics of signal assignment (postponed assignment) and see what you get.

Cross check via simulation as Jim suggests...

answered Jul 15 '13 at 22:36

So it seems that signal assigments are done at the end of the process, did I get it right? And Thanks! – triple fault Jul 16 '13 at 08:15

score 2 · Answer 2 · edited May 23 '17 at 12:30

You could just synthesize it yourself.

See also ffv3 http://www.cs.uregina.ca/Links/class-info/301/register/lecture.html which is almost the same.

Update
I was missguided by the missing formatting – in fact it actually is toggling on the falling edge as another answer already shows.

Although all asignments are done in sequence, signal assignments still happen at the end of the process, and thus temp_signal is half a clock cycle old (next falling edge) and does not contain the recently asigned value.

http://www.gmvhdl.com/process.htm
How does signal assignment work in a process?

score 2 · Answer 3 · answered Jul 16 '13 at 05:02

Separate the assignment to Q into it's own process statement with the same sensitivity list. The simulation models behavior will be identical although they vary in the number of processes.

DUT:
    process (CLK,RESET)
    begin
        if RESET = '1' then
            temp_sig <='0';
        elsif CLK'event and CLK ='1' then
            temp_sig <= I;
        end if;
--        Q <= temp_sig;
    end process;

QDEVICE:
    process (CLK, RESET)
    begin
        Q <= temp_sig;
    end process;

The edge sensitive storage device assigning temp_sig is clearly a positive edge clocked flip flop sensitive to CLK and asynchronously reset by RESET (high).

Is the QDEVICE process a synthesis target construct? It behaves as a follower latch to the temp_sig flip flop, but there is no indication as to the polarity of an enable. See IEEE Std 1076.6-2004 IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, 6.2.1.1 Level-sensitive storage from process with sensitivity list:

A level-sensitive storage element shall be modeled for a signal (or variable) when all the following apply:

c) There are executions of the process that do not execute an explicit assignment (via an assignment statement) to the signal (or variable).

Without qualification (by level) rule c is not met. Further in the original process you cite the behavior doesn't map to one of the IEEE Std 1076.6-2004 6.2 Clock edge specifications none of which include using an intermediary signal.

Brian is right it's a trick question. A flip flop with a follower-something-else providing delay. And the 'U' value in the simulation for q until an event on CLK or RESET should be telling.

enter image description here

score 0 · Answer 4 · answered Jul 15 '13 at 16:42

0

Have you simulated it? When does Q change and why? When do signals update? During a rising edge, does Q get the value of I? Make sure to simulate it.

answered Jul 15 '13 at 16:42

Jim Lewis

3,601
10
20

score 0 · Answer 5 · edited Nov 14 '15 at 03:58

Lets look at the following line of code:

    elsif CLK'event and CLK='1' then

CLK is your timing signal (aka the clock).

CLK'event is triggered when there is a change in the value of CLK. CLK='1' means that the clock is equal to high.

So if the clock has changed and it is currently in the high state then we will execute the code within this ELSIF statement.

We know that there are only 2 states for bit variables, so if CLK changed AND it changed to a high state then it was originally in a low state. This means that the code will only execute when the clock goes from low to high.

If you wanted to execute on a high to low trigger then you would change the statement to read like this:

    elsif CLK'event and CLK='0' then

Flip flop implementation with process. [VHDL]

5 Answers5

Linked