0

I am doing a project in Image processing using VHDL.It is an encryption process of one image using another key image.

I created an TYPE for image as

type image is array (1 to 256,1 to 256) of std_logic_vector(7 downto 0);

I used the file read option to read the image.i have to perofrm an exor operation between original image and key image,and some scrambling of pixels has to be done.

initially I declared images as signals. Even though I was getting correct output,running that program made my system to hang.So I converted all images into variables and got the output smoothly without any hanging issues.

But the problem was with the synthesis.Now the code does not get synthesised.I removed the file read and write portions.I ran the synthesis for one whole day.but still I am not getting the results.Why it is taking this much time and how to solve this problem??

MSD
  • 109
  • 1
  • 2
  • 12

1 Answers1

2

Are you trying to synthesize this beast? You are trying to generate an image that is 256x256x8 bits = 524k bits. That means that just to store ONE image you are using 524k registers. For a lot of FPGAs this is more than they have available! You need to think about your utilization of resources on your chip.

When doing image processing, you need to do your processing line-by-line. You can't store the entire image at once, unless you are using off-chip storage such as a DDR Memory or you carefully utilize internal Block RAM storage. When you process the image, you read out a row at a time, buffer it into a FIFO, then perform whatever operation you need to perform, and write the result back to DDR Memory or Block RAM.

Trying to keep the entire image in Distributed RAM is a BAD idea.

Russell
  • 3,384
  • 4
  • 31
  • 45
  • What if i am using signals instead of variable??whether same problem will occur ?? – MSD Oct 03 '13 at 14:06
  • 1
    Variables vs. Signals won't make a difference. The tools are still trying to synthesize 512k of Distributed RAM. Here's a post on SO about the difference: http://stackoverflow.com/questions/15485749/vhdl-variable-vs-signal – Russell Oct 03 '13 at 14:26