Verilog testbench for fifo

Question

Can anyone help me in writing verilog test bench code for the following code !. I have tried but it's doesn't work !. it's a code for fifo(first in first out) with a single clock. i use icarus simulator

fifo4:

`timescale 1ns/10ps

module fifo4(clk, rst, clr,  din, we, dout, re, full, empty);

parameter dw = 8;

input       clk, rst;
input       clr;
input   [dw:1]  din;
input       we;
output  [dw:1]  dout;
input       re;
output      full, empty;




reg     [dw:1]  mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire        full, empty;
reg     gb;


always @(posedge clk or negedge rst)
    if(!rst)    wp <= #1 2'h0;
    else
    if(clr)     wp <= #1 2'h0;
    else
    if(we)      wp <= #1 wp_p1;

assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;

always @(posedge clk or negedge rst)
    if(!rst)    rp <= #1 2'h0;
    else
    if(clr)     rp <= #1 2'h0;
    else
    if(re)      rp <= #1 rp_p1;

assign rp_p1 = rp + 2'h1;


assign  dout = mem[ rp ];


always @(posedge clk)
    if(we)  mem[ wp ] <= #1 din;


assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;


always @(posedge clk)
if(!rst)            gb <= #1 1'b0;
else
if(clr)             gb <= #1 1'b0;
else
if((wp_p1 == rp) & we)      gb <= #1 1'b1;
else
if(re)              gb <= #1 1'b0;

endmodule

@pat i'm stuck at writing the testbench code. its just for simulation seeing the waveforms using icarus — user3446601, Mar 21 '14 at 14:10

score 1 · Answer 1 · answered Mar 21 '14 at 14:28

1

There are examples of RAM testbenches simulated using Icarus on EDA Playground which you could use as a starting point:

Fundamentally you need to decide what you're trying to test, how to generate test vectors to exercise your FIFO and how to validate that your FIFO is behaving as intended. The latter could be a simple as looking at the waveforms but it is far better to build a self-checking testbench that doesn't require manual inspection.

Also it's worth pointing out that using #1 delays in your code is generally an indication that something is wrong.

answered Mar 21 '14 at 14:28

Chiggs

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I was going to point out the `#1` delays but they seem to turn up in questions in batches, I think there is at least one school which teaches verilog this way. – Morgan Mar 21 '14 at 14:36
@Morgan yes it's worrying - students should be taught the current technology but a lot of course material I've seen looks a decade out of date. For example VHDL records are commonly omitted and yet they were introduced in *1987*! – Chiggs Mar 21 '14 at 14:52

Verilog testbench for fifo

1 Answers1