Can I make a nested with-select-when statement in VHDL?

Question

I've yet to see anywhere show an example of this, and I've yet to need it until now.

I have 2 control signals, and I need to make a nested with-select-when statement for them. I can easily nest things with case statements, but I have recently realized that I need this bit of code outside of a process because it screws with the timing. Here is the code I currently have:

case OpcodeIn is =>
    when "000000" =>
        case FunctIn is =>
            when "00000" =>
             ...
            when "00001" ==>
             ...
        end case;
    when "000001" =>
        ...
end case;

Also, I cannot just concatenate like:

controlSig <= OpcodeIn & FunctIn;

and then use:

with controlSig select output <=
    ...

because the FunctIn is only valid depending on certain values of OpcodeIn. Thus it would only work if there was a wildcard character like:

"0010" when "000001***********";

score 2 · Answer 1 · answered Apr 01 '14 at 12:40

2

Try it, see if it works! There's no reason that the language prohibits this behavior. You're actually incorrect that VHDL does not support a case statement with Don't Cares. As of VHDL-2008, this feature is supported. See below for an example:

process (Request)
begin
  case? Request is
    when "1---" => Grant <= "1000" ;
    when "01--" => Grant <= "0100" ;
    when "001-" => Grant <= "0010" ;
    when "0001" => Grant <= "0001" ;
    when others => Grant <= "0000" ;
    end case? ;
end process ;

The one thing to note is that the more decode logic you add to this process, the harder it will be to meet timing.

answered Apr 01 '14 at 12:40

Russell

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Thank you. Okay that's good to know I can use a hyphen for a don't care inside a case statement, but I need it inside of a with-select-when statement, as that is my attempt at circumventing needing a process! So would it also work inside that? – krb686 Apr 01 '14 at 12:44
Is this a combinational process? Select assignments can only be used in a combinational process. Either way, you should give it a shot with VHDL-2008 and let us know if it worked. – Russell Apr 01 '14 at 12:46
It should be combinational, but I screwed it up and made it sequential. It is the control unit of a MIPS processor. – krb686 Apr 01 '14 at 12:47
Well it compiles properly, but it doesn't actually recognize the wildcard hyphens. Instead it always returns the designated value for *when others*. – krb686 Apr 01 '14 at 13:14
Is this the Select statement that you're trying that doesn't work? – Russell Apr 01 '14 at 13:42
1

Yes, the wildcard feature does not work inside of a with-select. According to this answer here, http://stackoverflow.com/questions/9205910/vhdl-std-logic-vector-wildcard-values, this feature is not present in the current version of Xilinx's ISE – krb686 Apr 01 '14 at 13:47
However I got what I needed by using a standard when statement – krb686 Apr 01 '14 at 13:48

score 2 · Answer 2 · answered Apr 01 '14 at 18:48

The concurrent form is:

with Request select?
  Grant <= "1000" when "1---",
           "0100" when "01--",
           "0010" when "001-",
           "0001" when "0001",
           "0000" when others ;

As noted above, it is unlikely this works in Xilinx tools. Please be sure to submit a bug report against Xilinx tools. Each bug report helps them understand the importance of implementing the new features. Some how they missed the market statistics that clearly show that VHDL is the dominant FPGA design and verification language.

The above code example is borrowed from: http://www.synthworks.com/papers/vhdl_2008_2012_2up.pdf

Can I make a nested with-select-when statement in VHDL?

2 Answers2