Printing packed structs in System Verilog

Question

I have a packed struct defined as shown below

typedef struct packed {
    logic bit1;
    logic [7:0] byte1;
} MyPackedStruct;

MyPackedStruct myPackedStruct;

Is there any SV built in function that I could use to print the structures similar to above but having many more fields, without having to write my own method to print each of the fields using a

$display(...,myPackedStruct.field_name)?

score 9 · Answer 1 · answered Jul 02 '14 at 14:26

9

You can use the %p formatting element.

$display("%p", myPackedStruct);

Output from Modelsim:

 # '{bit1:x, byte1:x}

See section 21.2.1.7 Assignment pattern format in the IEEE 1800-2012 SystemVerilog language spec.

answered Jul 02 '14 at 14:26

dwikle

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+1 Thanks for the section reference to the spec. I missed this section somehow. – Vissu Jul 03 '14 at 02:23

score 7 · Accepted Answer · answered Jul 02 '14 at 14:28

7

You can use %p - pretty print:

$displayb("%p",myPackedStruct);

'{bit1:x, byte1:xxxxxxxx}

which will print it as an assignment pattern, but you will not be able choose the fields or their ordering, or apply any other individual formating. %p is good for quick and easy displays, but most people eventually wind up writing a method to format it exactly the way they want it.

answered Jul 02 '14 at 14:28

dave_59

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This is also valid for printing dynamic arrays. – Joniale Dec 07 '20 at 08:53
You can use it for any unpacked array, but any large array you will probably want to format in some kind of loop. – dave_59 Dec 09 '20 at 21:28
Cannot edit this post: "Suggested edit queue is full" But $displayb should be $display – Bamban Jun 03 '21 at 09:24
@Bamban `$displayb` is what I wanted to get everything printed in binary radix. – dave_59 Jun 03 '21 at 18:00
OK! Sorry for the definitive comment I put, then. Do you know where I can find the doc about displayb in the LRM ? – Bamban Jun 04 '21 at 07:00
Section _21.2 Display system tasks_ in the [1800-2017 SystemVerilog LRM](https://ieeexplore.ieee.org/document/8299595%5DIEEE) – dave_59 Jun 04 '21 at 14:48

Printing packed structs in System Verilog

2 Answers2