Is it possible to use a process inside a 'case is when' structure?

Question

The answer is clear. Is it a legit programming way in VHDL? For example;

case (i) is
        when 0=>
             process() is begin
                counter:=0;
             end process;
end case;

Thanks in advance for replies.

Edit for Brian Drummond's reply:

I know it can usable selective blocks in cases. But in that blocks, lines are executed in order or simultaneously?

For example;

case (i) is
            when 0=>

                    if reset='1' then

                        giden_data<='0';
                        k:=0;
                        i:=0;
                        s_clk<='0';

                    elsif reset='0' and rising_edge(clk) then

                        giden_data<=CR(k);

                        if k<7 then

                        k:=k+1;

                        elsif k=7 then

                        giden_data<='0';

                        end if;

                        i:=0;

                    end if;
end case;

Is a synchronous process (like used in 'process'es) usable in the case statements or not? ISE gives an error for the code above which says;

Unexpected embedded clock statement in sequential description for signal <giden_data>.

I wonder the error causes from a synchronous code in case statement or something else in the block.

Answer 1

Short answer: no. case ... is is a sequential statement, and must be placed inside a process, not the other way around.

In VHDL-2008, you can put processes inside case ... generate statements, but this may not be what you want. It depends on what you're trying to accomplish.

edit for updated question

You wrote:

case (i) is
  when 0=>
    if reset='1' then
      giden_data<='0';
      k:=0;
      i:=0;
      s_clk<='0';
    elsif reset='0' and rising_edge(clk) then
      giden_data<=CR(k);
      if k<7 then
        k:=k+1;
      elsif k=7 then
        giden_data<='0';
      end if;
      i:=0;
    end if;
end case;

The proper structure for this is:

if reset='1' then
  giden_data<='0';
  k:=0;
  i:=0;
  s_clk<='0';
elsif rising_edge(clk) then
  case (i) is
    when 0=>
      giden_data<=CR(k);
      if k<7 then
        k:=k+1;
      elsif k=7 then
        giden_data<='0';
      end if;
      i:=0;
  end case;
end if;

And that entire block will need to be wrapped in a single process. This may not accomplish what you want, but the structure you're using won't work for various reasons.

Now, with VHDL-2008, you could switch to case ... generate, as I mentioned above, but that will have the consequence of requiring your case evaluation to be static at compile time, so if you're interested in switching your logic at runtime based on a signal value, you will need to expand/modify the above to suit your needs. (see also Brian Drummond's answer)

edit to respond to comment

You wrote:

Ok but i'm asking if i don't use process but use the code which i wrote inside the process in cases, is that lines execute in order or simultaneously?

You cannot use sequential code (case statements, if statements, etc.) outside of a process. Also, synthesized VHDL is not "executed" like software. What happens is that physical logic is inferred from the code, and by nature, they exist and operate simultaneously (physically, not algorithmically). As for how the algorithm effectively operates, it depends on your design.

For what you're trying to accomplish, though, why can't you just use a case statement inside a process?

process
begin
  case i is
    when 0 =>
      -- code that only operates when i = 0
    when 1 =>
      -- code that only operates when i = 1
    ...
  end case;
end process;

In what way does this not accomplish your goal?

Answer 2

No. However from your later comment

I want to make run specific blocks when they fit specific conditions.

you might get what you want from a Case statement inside a Process.

Process(clock,reset) is
   variable counter : integer;
begin
   if reset = '1' then
      counter := 0;
   elsif rising_edge(clock) then
      case (i) is
      when 0 =>
         counter := 0;
      when 1 =>
         counter := counter + 1;
      when 2 =>
         counter := counter - 1;
      when others =>
         null;  -- nothing happens to counter
      end case;
   end if;
end process;

In every clock cycle, the current value of i is tested and one of the specific blocks is executed. If that isn't what you are looking for, we'll need a better description.

The code works as if the lines selected by the Case are executed in order, and the process executes all lines in the selected block and completes immediately after the clock edge.

Note that signals and variables behave differently in a process : variables follow the rules you are familiar with if you have written software in a language like C. However signals behave differently, because they are the method for communicating between processes. See this Q&A for more information on how signals and processes work.

Answer 3

VHDL has with concurrent assign, somehow similar to the case as sequential statement, and the may look like:

with i select
  counter <=  0 when 0,
             -1 when others;