Verilog: Why can I not invert a wire?

Question

module hamming_code #( parameter TOTAL_LENGTH = 15,
                               parameter PARITY_BITS = 4
                           )
                (
                    //inputs
                    input [TOTAL_LENGTH-1:0] codeword,

                    //outputs
                    output [TOTAL_LENGTH-1:0] correctedWord
                //  output reg badData
                );
wire b;
assign  correctedWord = codeword;

assign  b = ~codeword[0];
assign correctedWord[0] = b;

endmodule

I am trying to invert the value of a single wire in an array of wires. However, whenever I do, that position becomes an 'X' instead of a 0 or 1. Why is this the case?

score 5 · Accepted Answer · answered Oct 26 '14 at 04:16

The three assign statements you have are all applied in parallel, not sequentially. You are assigning bit 0 of correctedWord twice, to opposing values in each assignment. If you have multiple assignments to one wire, there is a resolution function which determines the output. In your case there are two drivers, one driving a 1 and one driving a 0, which resolves to an X.

You want to do something like this:

assign  correctedWord[TOTAL_LENGTH-1:1] = codeword[TOTAL_LENGTH-1:1];
assign  correctedWord[0] = ~codeword[0];

Or this:

assign  correctedWord = {codeword[TOTAL_LENGTH-1:1], ~codeword[0]};

Verilog: Why can I not invert a wire?

1 Answers1