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I'm trying to compile a code similar to this: 

`define CORES_NUM 4
reg [1:0] core = 'h0;
reg [`CORES_NUM-1:0] result = 'h0;
integer i;

always @ (posedge clk) begin
   case (core)
      for (i = 0; i < `CORES_NUM; i = i + 1) begin       
         i: begin
            result[i] <= 1;
         end
      end
   endcase
end

Only one core is active at the moment. I expect that my code is equal to that: 

case (core)      
         0: begin
            result[0] <= 1;
         end
         1: begin
            result[1] <= 1;
         end
         2: begin
            result[2] <= 1;
         end
         3: begin
            result[3] <= 1;
         end
endcase

In other words, I need 'for loop' only for auto setting - if I change CORES_NUM, case states are automatically changed. But my code builds with errors. How can I use for loop in case statement?

Sharf
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  • No, I need it. I wrote the simplified code. At first, I select "core", then I run it with control signals. Control signals are special for each core so I need case statement. – Sharf Feb 17 '15 at 15:24
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    possible duplicate of [Generate block inside case statement in verilog or system verilog](http://stackoverflow.com/questions/25849445/generate-block-inside-case-statement-in-verilog-or-system-verilog) – Eugene Sh. Feb 17 '15 at 15:40

1 Answers1

0

Why not:

always @(posedge clk) if (core < `CORES_NUM) result[core] = 1;
dave_59
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