why is the output of JK flip flop red in simulation?

Question

I am posting a Code for JK Flip flop in VHDL language. the code is correct according to the JK flip flop circuit. but i got output as red line. can any one tell me the what is the problem with only JK flip flop only.

Programme: JK Flip Flop

----------=======NAnd Gate with three inputs=====---------------

library ieee;
 use ieee.std_logic_1164.all;
 entity nand_gate3 is port(
       A, B, C : in std_logic;
             F : out std_logic);
 end nand_gate3 ;


 architecture nandfunc3 of nand_gate3 is
  signal x : std_logic ;
 begin
      x <= A nand B ;
      F <= x nand C ;
end nandfunc3;

------====== END NANd GATE  with three inout ======--------

----=========NANd Gate with Two inputs==========------------
 library ieee;
use ieee.std_logic_1164.all;
 entity nand_gate2 is port(
          A, B : in std_logic;
             F : out std_logic );
end nand_gate2;

architecture nandFunc2 of nand_gate2 is
begin
      F <= A nand B ;
end nandFunc2;
------====== END NANd GATE  with three inout ======-
library ieee;
 use ieee.std_logic_1164.all;
 ENTITY  JK_flipflop IS PORT ( 
                     clk , J, K : IN  std_logic; 
                     Q , Q_bar  : OUT std_logic );
 END JK_flipflop ;  

 architecture JK_structure OF JK_flipflop  IS 
 ----===Compnents 
    COMPONENT nand_gate3 IS PORT (
                       A, B ,C  : IN std_logic ; 
                       F        : OUt std_logic );
    End Component ; 

    COMPONENT nand_gate2 IS PORT (
                       A, B   : IN std_logic ; 
                       F        : OUt std_logic );
    End Component ; 

    Signal X, Y , Qback ,Qbar_back: std_logic ; 
----== Structure
  Begin 

   U1: nand_gate3 PORT MAP ( J, clk, Qbar_back, X ); 
   U2: nand_gate3 PORT MAP ( K, clk, Qback    ,Y );
  U3: nand_gate2 PORT MAP ( X, Qbar_back  ,Qback); 
  U4: nand_gate2 PORT MAP ( Y, Qback  ,Qbar_back); 

   Q <= Qback;
    Q_bar <= Qbar_back;

END JK_structure ;

--------------------Test Bench for JK flip flop----===

 library ieee;
 use ieee.std_logic_1164.all; 

 entity jk_flipflop_tb is 
 end jk_flipflop_tb ;

   architecture tb of jk_flipflop_tb is
   ---====Jk_flipflop 
    component   JK_flipflop is  port(
                 clk,J , K  : in std_logic;
                 Q, Q_bar   : out std_logic);
   end component;
---===signals
   signal clk,J ,K , Q, Q_bar : std_logic;

   begin
    mapping:   JK_flipflop port map(clk, J, K, Q, Q_bar);

-------=========Process for Clcok ===========---------------
    process

 begin
    clk <= '1';
    wait for 5 ns;
    clk <= '0';
    wait for 5 ns;
   end process;
 --------===========Process for j,k inputs values=======--------------
 process

 begin
 -------===TEST 1
  J <= '0';
  K <= '1';
    wait for 20 ns;
  -------====TEST 2
   J <= '1';
   K <= '1';
   wait for 20 ns;
 -------====TEST 3
  J <= '1';
  K <= '0';
   wait for 20 ns;
 -------====TEST 4
   J <= '0';
   K <= '0';
  wait for 20 ns;

  end process;
end tb;
--------------------------------------------
 configuration cfg_tb of jk_flipflop_tb is
  for tb
  end for;
end cfg_tb;

---------======------

enter image description here

value is undefined, not 0 or 1! – 23ars Mar 03 '15 at 11:08 — 23ars, Mar 03 '15 at 11:08

Amir · Answer 1 · 2015-03-03T18:55:22.723

JK flip flops must have a reset port to initialize outputs, Otherwise because outputs (Q , Qbar) are set by themselves (feedback), if they don't have any initial value, they are always undefined. Then you should add a reset port to your design.

You can use the following code to get the correct result :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity JK_FF is
    port( 
        Reset  : in  std_logic;
        Clock  : in  std_logic;
        J,K    : in  std_logic;
        Q,Qbar : out std_logic
    );
end JK_FF;

architecture Behavioral of JK_FF is
    signal temp : std_logic;
begin
    process (Clock) 
    begin
        if rising_edge(Clock) then                 
            if Reset='1' then   
                temp <= '0';
            else
                if (J='0' and K='0') then
                    temp <= temp;
                elsif (J='0' and K='1') then
                    temp <= '0';
                elsif (J='1' and K='0') then
                    temp <= '1';
                elsif (J='1' and K='1') then
                    temp <= not (temp);
                end if;
            end if;
        end if;
    end process;

    Q <= temp;
    Qbar <= not temp;

end Behavioral;

Thank you amir,,, Plese can you correct the code for gate level. — Misal313, Mar 03 '15 at 14:22
VHDL is inappropriate for gate level, you really should use @amir code or an analog simulator. Beside, your nand3 should read x <= not (A and B and C); — Jonathan Drolet, Mar 03 '15 at 17:08
My thoughts as well (@Jonathan Drolet), but if you really have to use logic gates, you can synthesize my code in some synthesis tool (such as Xilinx Synthesis Tool) and click on "view schematic Technology". Output contains some LUTs, DFF, ... . (LUTs can be converted to basic logic gates) Then you can write your code with everything you see on the Schematic Technology window. — Amir, Mar 03 '15 at 17:36

score 0 · Accepted Answer · answered Mar 03 '15 at 11:11

0

Your logic seems to be faulty. The right logic is: Q = (J and Qbar_back) nand clk nand Qbar_back Qbar = (K and Q_back) nand clk nand Q_back

The and operation is a nand operation in your logic.

answered Mar 03 '15 at 11:11

omgBob

527
3
9

if you know the fault please correct it for me... thank you .@ omgBob – Misal313 Mar 03 '15 at 14:25

why is the output of JK flip flop red in simulation?

2 Answers2