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I very recently began experimenting with FPGAs. In researching things around the net I've noticed in several places that designs might use multiple separate PLL clocks of the exact same speed. Why is that?

One example I will give is this site: Parallella Linux Quick Start

They have their FCLK_CLK1 and FCLK_CLK2 both at 200MHz. Why is this recommended and not a single clock at 200MHz for both? Is it just customary to give each major component their own clock even if it is the same? Or am I missing something?

user3666197
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RobC
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    A couple possibilities are clock gating for power saving, separate clock networks each with lower fanout – Ben Voigt Mar 13 '15 at 04:51
  • Have you thought of asking someone involved in the Parallella project? There's also Xilinx User Guide 899, Vivado Design Suite User Guide, [I/O and Clock Planning](http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_2/ug899-vivado-io-clock-planning.pdf), where you'll find there's a Clocking Wizard. There are clock regions with associated BUFGs and I/O pins. At some point you likely want to trust the vendor (Xilinx) to know what they are doing. Look through the set of References in Appendix B. You're not likely to find an instant answer. –  Mar 13 '15 at 07:21

2 Answers2

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Beside the already mentioned reasons multiple other reasons exist why two PLL clocks of the same speed might exist.

Even if the frequency is exactly the same, differences might exist in clock phase or jitter. Using one PLL with fixed clock phase and another one with adjustable clock phase can be useful for proper sampling of external input signals or maintaining the correct phase difference between clock and output data. Techniques like that were especially popular before components such as IDELAY and ODELAY were widely available.

Crystal oscillators also will have small derivations from their marked value. If you have a communication link between two boards and both boards have their own oscillator, then one boards main clock might run at 200.01 Mhz and the other boards could run at 199.99 Mhz. In many cases both FPGAs will then their locally generated low-jitter clock as their main clock, but will also use the remote clock to sample incoming data. You can see this in ethernet PHYs: A 100 Mbit PHY usually has a 25 Mhz receive clock recovered from the input signal and a locally generated 25 mhz transmit clock.

Jan Lucas
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There are many reasons to use multiple clocks of the exact same speed. So I will just state a few. However i don't have any deep knowledge of your example.

  • Magic on FPGA.

Like stated in the comments a FPGA is a highly complex device. Only the vendor knows exactly what is happening there, so they might give you some advice, which can be weird.

  • Clock distribution.

If you have a design, with just one clock source, it is critical to route the clock correctly. The clock has to trigger everywhere at the same time, which is hard to manage for the PnR tool. Today's FPGAs don't usually have this issue.

  • Different IPs on one FPGA.

If you have different IPs/Designs, which you fuse on one FPGA, the IPs can use different clocks. If you want to split it later again, you will need multiple sources of the clock anyway. Besides, you are forced to implement some registers if you switch a clockdomain and during the merging of your IPs, you don't mix up evrything, which is a good design style. This also maybe the case of your example.

HDMI support is provided by an IP core from Analog Devices ...

  • Output.

Maybe the additional clock is only used as an output at some I/O Port.

  • Low-Power.

In today's CMOS technology, the most power is wasted on transitions (transistor switches) and static power-leakage (the damn thing is so small, it just leaks current). With multiple clock domain, you have the opportunity to have less transitions per second. Or you can switch off parts of your device completly.

hr0m
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