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I am developing a code on VHDL and I need to make subtraction operation on std_logic_vector. I tried to define and use the following libraries:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

then I defined signals like:

signal r0,r1,r2,r3,r4,r5,r6,r7: STD_LOGIC_VECTOR (19 DOWNTO 0);

then I wanted to do the following subtraction:

        r0 <= r0(16 downto 8) - r0(7 downto 0);

But it gives me error on the - operator. The error says:

Error (10327): VHDL error at euclidian_vhd_hls.vhd(84): can't determine definition of operator ""-"" -- found 0 possible definitions

Please help me to solve this issue.

Thanks a lot.

Jim Lewis
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eslam saad
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  • I removed your reference to std_logic_arith as if you have both numeric_std and std_logic_arith, your usage of unsigned in your solution below is ambiguous and would not analyze. – Jim Lewis Dec 21 '21 at 04:48

2 Answers2

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I found an answer to use the following syntax:

r0 <= std_logic_vector(unsigned(r0(16 downto 8)) - unsigned(r0(7 downto 0)));

I guided to this solution by this Stackoverflow question

Community
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eslam saad
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  • If you simulate, this get a run time error on initialization even though it analyzes and elaborates. The expression on the right hand side (length 9) does not have the same length as the target on the left hand side (length 20). IEEE Std 1076-2008, 14.7.3.4 Signal update, "If S is a composite signal (including a slice of an array), the effective value of S is implicitly converted to the subtype of S. The subtype conversion checks that for each element of S there is a matching element in the effective value and vice versa. An error occurs if this check fails." –  Jun 28 '15 at 22:38
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I think you logic doesn't work, becouse you apply r0 onn r0, it infinity loop. you need state it on process with rising or falling edge

Josef Polin
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  • This doesn't seem to address the question at all (for which the OP seems to have found an answer anyway). – Eiko Sep 21 '16 at 07:28