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I'm working with a RISC-V Rocket chip. I added some of my own signals and logic and wanted to see the values of existing signals in the Rocket chip that aren't already shown in the VCD waveform. How do I dump these signals in the VCD file?

Caylen Lee
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  • Are you saying that there are signals in your design that aren't showing up in the vcd waveform? Are you using the C++ backend? – Chris Sep 15 '15 at 22:12
  • Yes, there are signals not showing up in the vcd waveform. That said, I'm not familiar with the C++ backend. – Caylen Lee Sep 16 '15 at 10:17
  • Are these signals wires or somehow part of the synthesized result? – user2548418 Sep 16 '15 at 17:00
  • Can you clarify what you mean by part of the synthesized result? – Caylen Lee Sep 16 '15 at 17:37
  • By result I mean something that ends up in the verilog emitted by chisel. If a use a scala variable in chisel, it will not necessarily be emitted. In order to be emitted, it needs to serve a function in the design (a wire for example). – user2548418 Sep 16 '15 at 18:45
  • In other words, supposed inst is a 32-bit signal that is already dumped in the vcd, and I do "val test = inst(13)". test wouldn't show up unless I make it a wire or something like that? Secondly, why doesn't something like "val array = SeqMem(Bits(width=encRowBits), nSets*refillCycles)" show in the vcd waveform? Isn't interfacing with memory a function in the design? – Caylen Lee Sep 16 '15 at 20:09

1 Answers1

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There are a number of reasons a signal in Chisel will not show up in the vcd waveform.

First, your design isn't using the signal. Something like val test = inst(13) will be pruned and not emitted if nobody reads the test signal. I believe Chisel may have a debug(test) construct to force it to exist, but I'm not sure.

Second, signals may get renamed during elaboration and show up as different signals. Something like val a = b may mean that b doesn't show up in the waveform, but a does.

Third, typically Chisel signals not in the highest scope will not show up. For example, signals defined locally within when() statements.

Four, memories don't show up by default. They are typically too big to be feasibly dumped. If you are truly sure your memories aren't too big, you can pass a flag to Chisel called --vcdMem.

Chris
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