Extending MIPS datapath to implement SLL and SRL

Question

Here's the datapath:

So this seems like a pretty common question but I can't seem to find any answers on how to extend the datapath to implement SLL and SRL.

This is how I would think to do it but I'm not entirely sure:

It would need another mux right next to Read data 1 next to the register file. This mux would take Read data 1 (rs) and Read data 2 (rt) as inputs. It would select Read data 1 if we're not doing a shift operation, and it would select rt if we ARE doing a shift operation (since sll and srl use rt, not rs). This would then be fed into the ALU.

Next, we would need to branch Instruction[10:6] (the shift amount) off of Instruction[15:0], and Instruction[10:6] would then be fed into the other port of the ALU. Is this correct thinking?

score 3 · Answer 1 · answered Feb 23 '17 at 19:05

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This is sll on single cycle datapath, but i am not sure if the ALU now gets 5 instead of 4 bits control input. If u make sll then the first ALU input would be shamt and the second is the register to be shifted, ALU know if it must make shift because of instruction field, because it is a R-Type instruction. Then the shifted data will be saved in rd register. SLL SC datapath

answered Feb 23 '17 at 19:05

MUST_DIE

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I think this is the way to go. If you need 5 bit ALU control depends on how much ALU operations you already support.I also would feed "shamt" directly to ALU because a value of 0 is also vald. ALU can decide based on operation whether to use it or not. – lgnom Jan 03 '19 at 13:58

score 2 · Answer 2 · answered Dec 05 '15 at 01:03

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You need to modify the datapath for the SLL instruction, adding a input line to the ALU with the "shamt" field in order to determine de shift amount. The ALU will identify the SLL operation by the ALUop field. Modiffied datapath

answered Dec 05 '15 at 01:03

Seba Montini

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If you did this then what happens to the 2nd input to the ALU? The one after the mux. – izelkay Dec 07 '15 at 17:56

score 0 · Answer 3 · answered Mar 27 '19 at 03:21

You are going in the correct direction. As stated in one of the answers, there can be one additional port added to the ALU which will consider the shamt amount (bits [10:6]). There can be some internal hardware such as a MUX in the ALU which takes care of selecting either the shamt field or Read Data 2 from the output of register file.

Extending MIPS datapath to implement SLL and SRL

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