Verilog Error: Object on left-hand side of assignment must have a variable data type

Question

I'm trying to write a top-level module in Verilog that will open a water valve whenever a sensor reads values below a certain number.

Here is my code:

module ProjectDSD(alteraClock, sensorInput, openValve);

input sensorInput, alteraClock;
output openValve;

always @(sensorInput)
begin

if(sensorInput < 100)       //sensor value to irrigate at
begin

openValve <= 1;  //here

end

else
begin

openValve <= 0;  //here

end
end    
endmodule

Im getting an error saying:

Object "openValve" on left-hand side of assignment must have a variable data type

What am I missing? Also, which pins can I use on an Altera DE2-155 board to output a digital signal of only 1's and 0's for the the valve to open/close?

score 5 · Answer 1 · edited May 23 '17 at 12:30

5

s/output openValve/output reg openValve/

Outputs default to wire; you need a reg. See also this question.

edited May 23 '17 at 12:30

Community

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1

answered Dec 01 '15 at 19:58

EML

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score 1 · Answer 2 · answered Dec 01 '15 at 20:04

openValve is currently inferred as a wire. Add reg openValve; below output openValve; and your code will work.

Suggestions: It looks like you are following the IEEE1364-1995 non-ANSI coding style. Will still legal, you might want to change to the ANSI coding style, supported in IEEE1364-2001 and above.

Non-ANSI:

module ProjectDSD(alteraClock, sensorInput, openValve);

input sensorInput, alteraClock;
output openValve;
reg openValve;

ANSI:

module ProjectDSD(
  input alteraClock, sensorInput,
  output reg openValve);

For combinational blocks, it is recommended to use always @* (or the synonymous always @(*)) instead of always @(sensorInput). @* is an auto sensitivity list also added in IEEE1364-2001

score 0 · Answer 3 · answered Dec 01 '15 at 19:58

0

Try output reg openValve;.

For the second half of your question (which should really be a separate question) import this QSF file into your project. Any of the GPIO can be configured as outputs, and are accessible by the 40-pin header on the side.

answered Dec 01 '15 at 19:58

wilcroft

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That is not valid syntax according to any IEEE1364 or IEEE1800. Some tools allow it but it is a bad practice. I explained it on another question [here](http://stackoverflow.com/a/33747519/1959732) – Greg Dec 01 '15 at 20:12
Fair point, my bad. I (almost) always write ANSI, so I missed that the OP wasn't. – wilcroft Dec 01 '15 at 21:23
Hi Greg - I can't find anything in 1364-2005 which would make this code (or mine) invalid. In fact, 12.3.3 explicitly allows it - note "in the body of the module", and the `output reg` production. The confusion may be due to the text at the bottom of 12.3.3, which states that if the decl doesn't include a net or variable type, then it can be declared again in a net or variable decl, and the example on p175 shows this. – EML Dec 10 '15 at 15:39
And on the issue of "ANSI": the word ANSI doesn't appear in this context in 1364. It is a misnomer; various authors (incorrectly) thought that the new style was how things were done in "ANSI C", but they were wrong. You can't specify lists of objects in C in this context. – EML Dec 10 '15 at 15:42

Verilog Error: Object on left-hand side of assignment must have a variable data type

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