unable to enter if else statement

Question

I wrote a code like this:

   if (a) begin
   //some coding
   end
   else begin
   stage = 0;
           if (b) begin
                  if (stage == 0) begin
                  stage = 1;
                  end
                  else if (stage == 1) begin
                  stage = 2;
                  end
                  else begin
                  stage = 0;
            end
            else
            // some coding
            end
    end

When stage is 1, the code inside stage == 1 cannot perform. Is there anything wrong with my code?

What is the error? Can you show some stimulus? – sharvil111 Mar 11 '16 at 10:17 — sharvil111, Mar 11 '16 at 10:17
Is this inside an `always @*` or `always @(posedge clk)` ? – Morgan Mar 11 '16 at 13:12 — Morgan, Mar 11 '16 at 13:12

score 1 · Answer 1 · answered Mar 11 '16 at 13:18

Put like this, it cannot work. You have to put it in a process, i.e. always@(something).

//adding a signal needed
reg[1:0] stage_next;     

always@(*)begin//Means that everytime an event occurs in one of the signals used in the following code,
               //the code contained in this process will be executed
    if (a) begin
   //some coding
    end
    else begin
    stage = 0;
            if (b) begin
                  if (stage == 0) begin
                  //stage = 1;//this assignement will produce a combinatorial loop
                            //when the value of 'stage' changes the process(always@(*))
                            //will be re-executed. You have to assign another signal(stage_next here)
                  stage_next = 1
                  end
                  else if (stage == 1) begin
                  //stage = 2;//Same here
                  stage_next = 2;
                  end
                  else begin
                  //stage = 0;//Same here
                  stage_next = 0;
            end
            else
            // some coding
            end
    end
end
//The other process where stage will take the value of stage_next should be synchronous
//It will break the combinatorial loop
always@(posedge clk)
  stage <= stage_next;

score 0 · Answer 2 · edited May 23 '17 at 10:27

0

The blocking assignment stage = 0 before if (b) is forcing stage to zero before the stage == 1 condition is evaluated.

Use non-blocking assignment (<=) to all stage assignments and you should get the expected behavior. See How to interpret blocking vs non blocking assignments in Verilog?
Your code block must be within an sequential block (clock triggering, ex: always @(posedge clk))

edited May 23 '17 at 10:27

Community

1
1

answered Mar 11 '16 at 18:04

Greg

18,111
5
46
68

score 0 · Answer 3 · answered Mar 15 '16 at 22:33

I'd say your indentation is misleading, try instead:

   always @(*)
   if (a) begin
   //some coding
   end
   else begin
           stage = 1;
           if (b) begin
                  if (stage == 0) begin
                      stage = 1;
                  end
                  else if (stage == 1) begin
                      stage = 2;
                  end
                  else begin
                      stage = 0;
                  end
            end // Your code did not have this end
            else begin // This begin was also missing
            // some coding
            end
    end

So I think you are saying if you have that code, then you don't see stage == 2??? Because without those code modifications you'll have the else binding to an unexpected if

unable to enter if else statement

3 Answers3