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I used the following code to instantiate 2-D memory in a verilog

reg  [15:0] data_pattern_even [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

reg  [15:0] data_pattern_ev [3:0] = {16'hFFFF,16'hFFFF,16'hFFFF,16'hFFFF};

This instantiation worked all right in Simulation but failed to work when actually synthesised and RTL analysis done

Can anyone elaborate to me as in how that is possible?

Ananth Krishna
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  • What is the error/warning? – sharvil111 Jun 17 '16 at 08:17
  • No error . Just that in the RTL , all vaues of data_pattern_even arent FFFF . 1st one is FFFF and rest all are zero – Ananth Krishna Jun 17 '16 at 09:07
  • FPGA or ASIC synthesis? if FPGA can you list which FPGA and tool versions your using. – Morgan Jun 17 '16 at 09:15
  • artix - 7 xc7a35 and vivado 2014.2 . I heard from my friend that initialization in verilog has to be done on certain condition e.g reset . might that be the reason ? – Ananth Krishna Jun 17 '16 at 09:38
  • See [UG901](http://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_2/ug901-vivado-synthesis.pdf) for how to describe RAMs and ROMs for Xilinx Vivado synthesis in Verilog (or VHDL). – Paebbels Jun 17 '16 at 12:50