I currently have a very, very basic DDS core(?) with a counter, tuning word, and sine LUT that outputs 16 bit values to correlate with a sin value for a DAC. I am using the Nexys 4 DDR board and my DAC is a peripheral module designed exclusively for FPGAs. If its a 16-bit DAC, why does it have 6 pins, only 4 of which are for data? And how should I send the binary information from my 16-bit generated sin value to the DAC in order for the DAC to do a successful conversion?
Here is my code (I know its rudimentary, please forgive the mistakes, I will work them out once I properly know how to interact with the DAC!)
module sin_LUT(
input clk,
input [0:3] M,
input rst,
output reg [16:0] data_out,
output reg [32:0]test
);
//counter
//declaring constant
integer i;
integer int_M;
always @(M)
int_M = M;
always @(posedge(clk))
begin
if (rst)
i <= 0;
else if (i >= 29)
i <= 0;
else
i <= i + M;
end
//testing purposes
always @(i)
test = i;
//sine LUT
always @(i) begin
case (i)
0: data_out = 16'D32768;
1: data_out = 16'D39812;
2: data_out = 16'D46526;
3: data_out = 16'D52598;
4: data_out = 16'D57742;
5: data_out = 16'D61718;
6: data_out = 16'D64341;
7: data_out = 16'D65487;
8: data_out = 16'D65103;
9: data_out = 16'D63208;
10: data_out = 16'D59889;
11: data_out = 16'D55302;
12: data_out = 16'D49661;
13: data_out = 16'D43230;
14: data_out = 16'D36310;
15: data_out = 16'D29225;
16: data_out = 16'D22305;
17: data_out = 16'D15874;
18: data_out = 16'D10233;
19: data_out = 16'D5646;
20: data_out = 16'D2327;
21: data_out = 16'D432;
22: data_out = 16'D48;
23: data_out = 16'D1194;
24: data_out = 16'D3817;
25: data_out = 16'D7793;
26: data_out = 16'D12937;
27: data_out = 16'D19009;
28: data_out = 16'D25723;
29: data_out = 16'D32768;
default: data_out = 16'b0000111100001111;
endcase
end
endmodule