Curly braces in verilog

Question

I was looking through a program and found the following code:

{a2, a1} <= {a1, b};

I am not sure whether the program that I'm going through is written in Verilog or SystemVerilog. I know the curly braces are used for concatenation operation in Verilog, but then I don't quite follow what kind of concatenation is being done here. Also since I'm not sure whether the given snippet is in Verilog or SystemVerilog, I'm left confused with the code. Also does curly braces denote another operation in SystemVerilog…?

Thanks in advance

Possible duplicate of [What do curly braces mean in Verilog?](http://stackoverflow.com/questions/2102746/what-do-curly-braces-mean-in-verilog) — Qiu, Aug 11 '16 at 14:21

score 6 · Accepted Answer · answered Aug 11 '16 at 12:29

This is just concatenation treating the Left and right hand side as one variable each. SystemVerilog 2009 replace Verilog, so is backwards compatible with most (all?) syntax.

For example

wire [0:0] l1;
wire [2:0] l2;
reg  [1:0] r1;
reg  [1:0] r2;

assign {l1,l2} = {r1,r2} ;

Is the same as

assign l1[0] = r1[1];
assign l2[2] = r1[0];
assign l2[1] = r2[1];
assign l2[0] = r2[0];

Curly braces in verilog

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