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I'm doing a simple project of taking 100 numbers from an external memory (one by one), doing a simple arithmetic to that number (like adding 1) and returning it to another memory.

I successfully did that project "representing" a memory in verilog code, however I want now to synthesize my design but using the SDRAM of the board. The way I load data to the SDRAM or what I do with the resulting data outputted again to the SDRAM is irrelevant for my homework.

But I just can't understand what to do, all the information in internet takes me to the utilization of NIOS-II. Considering I have to load data to the SDRAM to make it able to serve me, and other reasons, maybe, is that NIOS-II is the most recommended way to do this? Can be done with out it, and would it be more practical?

sujeto1
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1 Answers1

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this might not be the place to have your homework done. Additionally your question is very unclear. Let's try anyway:

I successfully did that project "representing" a memory in verilog code

I assume that you mean that you downloaded a model corresponding to the memory you have on your board.

taking 100 numbers from an external memory

I wonder how you do that. Did you load some initialization file or did you write the numbers first? In case of the first: this will not be synthesized and you might read random data, you should refer to the datasheet of your memory for this. If you expect specific values, you will need to write them to memory during some initialization procedure.

Of course you will need the correct constraints for your device. So I'd suggest that you take the NIOSII example, get it up and running and get rid of the NIOSII in a next step. At least you will be sure that the interfacing between controller and sdram is correct. Then read the datasheet of the controller. Probably you have a readstrobe, write strobe, data in, data out port, some configuration, perhaps a burstlength. If you need help with that you'll need to come up with a more specific question

chrisvp
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  • "taking 100 numbers from an external memory" I have not used the external memories from the development board. I did a "simulation" or "representation" in a different file, where I load the data trough the command $readmemb, but this is not synthesizable this is only to test. I tested and It works fine, but now I want to pass the design into the proper DE1-SOC and I think I no longer can use $readmemb, but I have to learn to use the SDRAM in the board. An schoolmate have told me for me to do this, isn't necesary to use NIOS-II, using the megawizard and writting the correct verilog is enough. – sujeto1 Sep 19 '16 at 10:21
  • I thought `$readmemb` was synthesizable for loading memory defaults on FPGA. – Morgan Sep 19 '16 at 11:03
  • @Morgan: No. Refer to this discussion: http://stackoverflow.com/questions/4321067/is-readmem-synthesizable-in-verilog some synthesis tools are able to set these initial values on synthesized logic. The SDRAM is another story. – chrisvp Sep 19 '16 at 18:37
  • @sujeto1: pseudocode: if reset then init := 0; elsif clock: if init = 0 then for i in range(0 to 100) write value to address i if i = 100, init := 1; else do normal stuff, init is done – chrisvp Sep 19 '16 at 18:37
  • @chrisvp what is this for? – sujeto1 Sep 22 '16 at 07:11
  • @sujeto1: it describes (p)reset functionality for your sdram in answer to your question – chrisvp Sep 22 '16 at 07:17
  • @Morgan you meant to say internal ram of FPGA? correct? – sujeto1 Sep 28 '16 at 06:28
  • @sujeto1, yes internal ram of FPGA, but I am not an FPGA person, and only going from the comments I had picked up from other people. The example chrisvp links to says it depends on your toolset as to whether it is synthesizable. With verilog the is no definition of what is and is not synthesizable! different tool (versions) support different constructs. – Morgan Sep 28 '16 at 07:08