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I am attempting to use Yosys for a project of mine, but I am confused about the FSM detection.

I read this post: FSM export using Yosys

My question is about the state transitions detected from the Verilog file by Yosys. On the post that the link above points to, I don't see any way to transition from state 1 to state 3; however, in the generated graph there is. How is this? Thanks in advance.

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Abraham McIlvaine
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1 Answers1

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The state names are arbitrarily assigned. They do not encode the numeric value of the state register that corresponds to the state. Looking at the diagram and the original Verilog code, I'd say the mapping is as follows for that example:

s0: state == 0
s1: state == 2
s2: state == 1
s3: state == 3
CliffordVienna
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    Note that many CAD tools may remap your FSM assignments if a) you parameterize the state names/values, and b) don't directly access individual state bits. This lets the tool optimize the state transitions (minimize the number of bits changing per transition), as well as let you change your encoding scheme (count to one-hot, for example) on the fly. YOSYS assigning names this way isn't unreasonable. – wilcroft Sep 26 '16 at 20:31
  • Thanks a lot. I had a feeling I was overlooking something. – Abraham McIlvaine Sep 27 '16 at 15:57