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I have a piece of code that needs to be executed after another. For example, I have an addition slv_reg2 <= slv_reg0 + slv_reg1; and then I need the result subtracted from a number. 

architecture IMP of user_logic is

signal slv_reg0                       : std_logic_vector(0 to C_SLV_DWIDTH-1); --32 bits wide
signal slv_reg1                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3                       : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal flag                           : bit := '0';

begin

  slv_reg2 <= slv_reg0 + slv_reg1;
  flag <= '1'; 

process (flag)
begin
  IF (flag = '1') THEN
    slv_reg3 <= slv_reg0 - slv_reg2;
  END IF;  
end process; 

end IMP;

I haven't tested the code above but I would like some feedback if my thought is correct. What is contained in the process doens't need to run in sequence, how can I make this part also run in parallel?

In summary, I have two chunks of code that need to be executed in sequence but the code itselft should run in parallel.

--UPDATE--

begin
slv_regX <= (slv_reg0 - slv_reg1) + (slv_reg2 - slv_reg3) +(slv_reg4 - slv_reg5); --...etc
process(clk) -- Process for horizontal counter
begin
if(rising_edge(clk)) then
  if(flag = 1) then
    flag <= 0;
  end if;
end if;
end process;
traveller
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1 Answers1

2

It's concurrent, not parallel. Just use intermediate signals

I am afraid your thought process about VHDL is not entirely correct. You acknowledge the first assignment happening 'in parallel', but you must realise that the process is also running concurrently with the rest of the statements. Only what happens inside a process is evaluated sequentially - every time any of the signals in the sensitivity list change.

I need to make a lot of assumptions about what you need, but perhaps you're just after this style:

c <= a + b;
e <= d - c;

The signal e will contain d-(a+b) at all times. If you don't immediately understand why - this is where the difference between concurrent and parallel comes in. It is being continuously evaluated - just like if you'd hook the circuit up with copper wires.

If what you actually need is for something to happen based on a clock - you're really not there yet with your example and I recommend looking up examples and tutorials first. People will be happy to help once you provide VHDL code that is more complete.

Issues in your example

Assuming you are intending to write synthesisable VHDL, there several problems with your code:

  • Your process sensitivity list is not correct - you would either make it sensitive to only a clock, or to all the input signals to the process.
  • You are both initialising your 'flag' to '1' and assigning it a '0' in concurrent code, that doesn't make sense.
  • Signals ..reg0 and ..reg1 are not assigned. If they are inputs, don't declare them as signals.
  • You have named your signals as if they are anonymous numbered 'registers', but they are not registers, just signals: wires! (if ended up with this style because you are comparing to Verilog - let me argue that the Verilog 'reg' regularly don't make sense as they often end up not being registers.)

Try it

I haven't tested the code above but

You really should. Find code examples, tutorials, go and play!

Casperrw
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  • Thank you. What I want to achieve is for a microprocessor to send and fill some registers. Then perform some calculations and change a flag indicating the calculations are complete. I updated my original post with a code block which I think it's very close to my needs (just got home and i'll test it asap). The processor sends data and marks a flag register as '1' indicating that every data have been send. As soon an the calculations are performed the hardware will change the flag to '0' so the cpu can poll it. I am not sure if `slv_regX <= (` should be in or out of the process. – traveller Oct 24 '16 at 11:16
  • The operator <= is for concurrent assignments outside of a process. Can't you make the whole thing in concurrent code, without a process? Your update now has the problem that if flag is assigned, flag tries to change itself to zero instantaneously. This is not normal synthesisable VHDL. – Casperrw Oct 24 '16 at 11:34
  • Well, the cpu should wait for the calculations to be completed before it reads `slv_regX` register. I could put the calculations outside of the process but I need a flag to poll. Again I updated the code block. – traveller Oct 24 '16 at 11:40
  • Maybe I could use the `wait for clk_period` to ensure that the concurrent statement outside of the process is complete. – traveller Oct 24 '16 at 11:43
  • That's not normally synthesisable. Would it make more sense to have a clocked process? Because it looks like you want a one-bit register to keep track of a flag. Example of such a process: http://stackoverflow.com/a/9990133/4614812 – Casperrw Oct 24 '16 at 12:30
  • I think you want to add an external signal to set/reset the flag. Why don't you try it out... – Casperrw Oct 24 '16 at 14:25
  • What I call flag will be a slv_regX register set to 1 by the cpu and set to 0 by the vhdl logic. Nevertheless, i'm generating the netlist atm. – traveller Oct 24 '16 at 14:46