How to use the input's values in "always" definiton in Verilog

Question

I got the problem with using the input's value in Verilog. I write:

module reg_vector (INPUT, ICLK, IENBL, NR, OUT);
parameter k = 6;
parameter n = 3;
input [(8*k)-1:0] INPUT;
input ICLK;
input IENBL;
input [n-1:0] NR;

reg [n-1:0] temp;
output reg [7:0] OUT;

always@ (temp, posedge ICLK)
begin
    if (IENBL)
        begin
            OUT = INPUT[temp*8 : temp*8+8];
        end
end

endmodule

But got the error:

Error (10734): Verilog HDL error at reg_vector.v(25): temp is not a constant

How should I fix it? Thank you)

score 0 · Answer 1 · answered Nov 08 '16 at 16:57

0

Even if your vector is always 1 byte wide, the tool understands it as a variable size and it does not know how to deal with it. (you also inverted the indexes temp*8 and temp*8+8 in the vector selection)

Another way to do it is to use the shift operator

OUT = INPUT >> (temp*8);

This should work as OUT will take the lower 8bits of the shifting by 8*temp of INPUT

answered Nov 08 '16 at 16:57

Krouitch

596
3
13

Well, the error has gone, but i am not sure that the shift operator is solution. I need to connect the input legs with the output, depends on the NR input. I mean if the NR = 0 OUT = IN[7:0] And if NR = 1 OUT = IN[15:8] – Андрей Боровилов Nov 08 '16 at 17:23

score 0 · Accepted Answer · edited May 23 '17 at 11:48

INPUT[temp*8 : temp*8+8] does not work because the : range syntax requires both sides to be a constant.
What you want is to use the +: array slicing: INPUT[temp*8 +: 8] The left hand side of +: allows variables and represents the starting index. The right hand side is the width and must be a constant. For more on +: see Indexing vectors and arrays with +:

Other issues:

Remove temp from the sensitivity list.
temp needs to be assigned to something
OUT should be assigned with non-blocking (<=) not blocking (=) since it is sequential logic.

always @(posedge ICLK) // no temp in sensitivity list
begin
  if (IENBL)
  begin
    OUT <= INPUT[temp*8 +: 8]; // non-blocking and +:
  end
end

How to use the input's values in "always" definiton in Verilog

2 Answers2