I have designed a 16*16 multiplier. (operating at the frequency of 1550 MHz) I then use the same multiplier to perform three multiplications in series by putting registers at input which are used to change input operands. The result of the multiplications are stored in the registers. When three multiplications are performed in series, the frequency reduces to 500 MHz.I want to avoid the decrease in frequency and want to operate it at the frequency of single multiplier.
Since the single multiplier requires certain clock cycles to complete the operation, we therefore wait for few clock cycles before giving multiplier the new operands. A counter in used for this purpose. The counter counts the clock cycles and provides the delay necessary to complete multiplication.
The process is completed as follows: The first multiplication is started, then we wait for few clock cycles to compute the result, the result is then stored in the register and multiplier is provided with new operands, again the multiplier needs some clock cycles, this process continues three times. I just want this whole code to work at the frequency of single multiplier that is almost 1500 MHz.
The code is given below
////3 multiplications are carried out in this module
`define m 11
`define mbar 245
module test_mul(a,b,clk,reg2,reset);
input [15:0] a,b;
input clk,reset;
output reg [31:0] reg2;
reg [15:0] x,y;
reg [31:0] reg0,reg1;
reg [5:0] count;
wire [31:0]p;
test_mul16 a1 (x,y,clk, p);
always @ (posedge clk)
begin
if (reset)
begin x <= a; y <= b; count= 6'd0; end // first operands given
else begin // and counter started
if (count == 11) // first multiplication completed
reg2 <= p; // result moved to register
if (count == 12)
begin x <= reg0[15:0]; y <=`mbar; end // new operands
if (count == 27) // second multiplication completed
reg1 <= p; // second result to register
else if (count == 28)
begin // new operands for 3rd multiplication
x <= reg1[15:0];
y <= `m;
end
else if (count == 39) // multiplication completed
begin
reg2 <= p; // result moved to register
end
count = count+1; // counter incremented
end
end
endmodule
//// this multiplier operates at a frequency of 1550 MHz
//// This is then called in the upper module
module test_mul16(a,b,clk,reg2);
input [15:0] a,b;
input clk;
output reg [31:0] reg2;
reg [31:0] reg0, reg1;
always @ (posedge clk)
begin
reg0<= a*b;
reg1<=reg0;
reg2<=reg1; // just to increase some clock cycles- nothing else
end
endmodule
