fpga programming using verilog

Question

Case statement in verilog. I don't understand how this code works

 if(cpld_cs & cpld_we)
            begin
                case(ifc_a27_31)
                    `RSTCON1:   begin
                                    sw_rst_r <= ifc_ad0_7[0];
                                    ddr_rst_r <= ifc_ad0_7[1];
                                    ec1_rst_r <= ifc_ad0_7[2];
                                    ec2_rst_r <= ifc_ad0_7[3];
                                    xgt1_rst_r <= ifc_ad0_7[6];
                                    xgt2_rst_r <= ifc_ad0_7[7];

Welcome to Stack Overflow. Please take few moments to take a [tour] and also read [ask] to get better answers for your questions. — Marek Vitek, Jul 11 '17 at 12:40

Marek Vitek · Answer 1 · 2017-07-11T13:18:28.697

1

Just look up documentation. I am no verilog expert but checking documentation you can get that

            case(ifc_a27_31)
                `RSTCON1:   begin

is just simple case where if value of ifc_a27_31 is RSTCON1 then commands

                                sw_rst_r <= ifc_ad0_7[0];
                                ddr_rst_r <= ifc_ad0_7[1];
                                ec1_rst_r <= ifc_ad0_7[2];
                                ec2_rst_r <= ifc_ad0_7[3];
                                xgt1_rst_r <= ifc_ad0_7[6];
                                xgt2_rst_r <= ifc_ad0_7[7];

are getting executed.
And of course

 sw_rst_r <= ifc_ad0_7[0];

is just non-blocking assignment.

Information I took from Case Statement and What is the difference between = and <= in verilog?

edited Jul 11 '17 at 13:18

answered Jul 11 '17 at 12:39

Marek Vitek

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Thanks for your effort. – HAREESH Jul 11 '17 at 13:08
this is **not** `just assignment`. It is the `non-blocking` assignment which has a specific semantic. Please check verilog manual. – Serge Jul 11 '17 at 13:15
@Serge Yes I know, and it is obvious from link I added. I will correct that. Thanks. – Marek Vitek Jul 11 '17 at 13:17

score 0 · Answer 2 · answered Jul 11 '17 at 13:12

verilog case syntax consists of a case expression or selector expression (ifc_a37_31) and case items with label expression (macro RSTCON1 in your case) and action items. When afr_a37_31 matches the value of the macro, the statements in the begin .. end block will be executed sequentially.

The case statement might have multiple case items, the first one which matches the selector will be active and its block will be executed.

There is also a default clause which will get executed if no matches are found.

Now in your case it looks like this is a part of a latch or a flop definition, since 'non-blocking' assignments are used there. It is ok to miss some conditions and/or the default statement in such a case.

you might see other variants of the case statement, like casex or casez. Syntax for all of them is similar, the difference is in the ways the selector is compared to the label.

in system verilog there are more, like unique of priority cases or case inside.

So, you need to go through a tutorial to get more information about all this.

fpga programming using verilog

2 Answers2