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I have to use the Cadence program suite to complete a Verilog class assignment and I'd like to know why $display statements in the very simple mock-testbench I have created do not produce output in the SimVision console window.

My workflow goes like this: I have created a cell with the following functional view:

module tesbench ( );
  initial begin
    $display("RUNNING TESTBENCH");
    $finish;
  end
endmodule

I have then invoked NC-Verilog, initialized and netlisted and simulated the cell which opens the SimVision console window. Running the simulation then produces the following output:

ncsim> run
Simulation complete via $finish(1) at time 0 FS + 0
/home/path/to/verilog/file.v:4      $finish;
ncsim>

So $display output is not shown. This seems like a very simple problem but I cannot for the life of me figure out what I'm doing wrong.

halfer
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Peter
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  • That's did not solve it, I'm new to both Verilog and Cadence so I'm not sure whether this is even a problem with the code or if I'm not using the program suite correctly. – Peter Sep 03 '17 at 17:41
  • So this 'works for me' with SimVision.. What version are you using and how are you invoking the tool? – Brian Magnuson Sep 03 '17 at 18:21
  • I am also able to print the message. Which version are you using? – Karan Shah Sep 04 '17 at 05:57
  • Sorry for the late answer, I'm using SimVision 14.10-s004. I'm simply starting the tool from the main Virtuoso window via Tools->NC-Verilog and then clicking on Run, Generate Netlist and Simulate (Interactive with all options selected). I then issue the "run" command in the "Console SimVision" Window. To be honest I'd rather be doing all this from a terminal but it's difficult to find the right guides on these tools. – Peter Sep 05 '17 at 21:05

1 Answers1

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Okay, so I have just been able to speak with an instructor and he told me that this is a known problem with the installation and that there is currently no work-around (the programs are running on a server administrated by the university).

Peter
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