I'm doing an image processing project on Zedboard Zynq evaluation board, using the FPGA built on it. I have written the image processing block using HLS and created the IP with both input and output as AXI4 streams with width 8.
How do I read a JPEG image on my PC and send it as an AXI4 stream to this IP block, and output it back to show it on my PC screen ?
Are there any existing IPs which accomplish this ?
P.S. The FPGA board is connected to my PC via JTAG cable, in case it's relevant.
The exchange of image data between the programmable logic (PL) and the processing system (PS) of the Zynq, can be established using direct memory access (DMA)/video direct memory access(VDMA).
This functionally is provided by Xilinx as an IP core. This IP core implements the receiving and transmitting of image data on PL side as an AXI stream. On PS side the DMA can be made accessible by using the linux UIO. For this purpose you have to modify the device tree node of the DMA IP core in the device tree of the ARM core. If this is done, the DMA is available under /dev/ in the linux system. Now it can be mapped to the user space using mmap(). By configuring the DMA, a memory area in the RAM of the PS has to be assigned to it. This memory area is used to implement a so called stream buffer. The DMA core uses this stream buffer to read or write image data. At the same time a linux application can access this memory area. This allows exchange of data between PS and PL. A detailed description of the individual registers and the configuration procedure can be found in Xilinx's AXI DMA/VDMA product guide. As far as the image data is available in the user space, the Ethernet connection could be used to send the image to the host PC. The JTAG connection is not the proper way to exchange image data between a host PC and the Zed board.
