Verilog behavior of IF statement with invalid value in condition

Question

If IF-statement in Verilog has invalid value in condition, only else branch is evaluated. (In simulation.)

For example below in module SimpleIfStatement2b if a = 1'bx: b=0'b1

I was searching in Vegilog-2005 standard for this behavior and and can not find it.

Is this behavior a part of standard or it is only in implementation of iverilog simulator? Is this also a case in VHDL/SystemVerilog/SystemC? Where is standard describing this?

module SimpleIfStatement2b(input a,
        output reg b
    );

    always @(a) begin: assig_process_reg_d
        if (a) begin
            b <= 1'b0;
        end else begin
            b <= 1'b1;
        end
    end
endmodule


module main;
    reg a;
    wire b;

  SimpleIfStatement2b DUT (
    .a(a),
    .b(b)
  );

  initial begin
    a = 1'bx;
    repeat(1) #10;
    a = 1'b0;
    repeat(1) #10;
    a = 1'b1;
    repeat(1) #10;
    a = 1'b0;
    repeat(1) #10;
    a = 1'bx;
    repeat(1) #10;
    a = 1'b1;
    repeat(1) #10;
    a = 1'bx;
    repeat(10) #10;

  end

  initial begin
    repeat(10) #10;
    $finish;
  end

  initial
    $monitor("At %t, a=%b, b=%b,", $time, a, b, ); 
endmodule

http://tpcg.io/nAY75e

stdout:

$iverilog -o main *.v
$vvp main
At                    0, a=x, b=x 
At                   10, a=0, b=1 
At                   20, a=1, b=0 
At                   30, a=0, b=1 
At                   40, a=x, b=1 
At                   50, a=1, b=0 
At                   60, a=x, b=1

in conditional statements 'x' is always converted to '0' and is 'false'. This is a standard verilog behavior. — Serge, Feb 25 '18 at 17:10
Yes it is duplicate, I did not know that verilog adds a comparison with 1 and I accidentally posted an example where this comparison was explicitly added. — Nic30g, Feb 25 '18 at 17:38

score 2 · Accepted Answer · answered Feb 25 '18 at 17:24

2

IEEE standard Section 9.4, Conditional statement. Second paragraph:

answered Feb 25 '18 at 17:24

Oldfart

6,104
2
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score 0 · Answer 2 · answered Feb 25 '18 at 17:18

It's standard behavior.

If an 'if' condition is evaluated as False, then it will proceed to run the 'Else' section.

Think of it like this:

If I tell you:

"If you are older than 100, High Five! Otherwise, do a starjump."

Only if you're older than 100 will I high five you. Otherwise (which is like the 'Else' section) I will tell you to do a starjump. You won't do a starjump if you're over 100 as you've passed the 'If' condition, but you will do a starjump if you aren't older than 100 (i.e. the 'if' condition is false).

I accidentally posted wrong example, I was asking where is in standard written how invalid conditions evaluates. — Nic30g, Feb 25 '18 at 17:42

Verilog behavior of IF statement with invalid value in condition

2 Answers2