Why don't signals update inside process?

Question

I am trying to insert 4 groups of 16 bits to form 2 numbers of 32 bits (in IEEE 754 format). This is my code:

  entity insert is
    Port (
           Clk : in STD_LOGIC; 
           Enter : in STD_LOGIC;
           Number: in STD_LOGIC_VECTOR (15 downto 0);

           Sign_A : out STD_LOGIC;
           Exponent_A : out STD_LOGIC_VECTOR (7 downto 0);
           Mantissa_A : out STD_LOGIC_VECTOR (23 downto 0);

           Sign_B : out STD_LOGIC;
           Exponent_B : out STD_LOGIC_VECTOR (7 downto 0);
           Mantissa_B : out STD_LOGIC_VECTOR (23 downto 0)
           );
end insert;

architecture Behavioral of insert is

begin
proc: process(Enter,Number,Clk)
--variable cnt :integer :=0;
variable cnt: integer := 0;
variable number_A:std_logic_Vector(31 downto 0):=(others =>'0');
variable number_B:std_logic_Vector(31 downto 0):=(others =>'0');
variable intermNumber:std_logic_vector(15 downto 0);
begin

if(rising_edge(Clk))then
    if (Enter ='1' ) then
        case cnt is
        when 0=> number_A(31 downto 16) := Number;
        when 1=> number_A(15 downto 0) := Number;
        when 2=> number_B(31 downto 16) := Number;
        when 3=> number_B(15 downto 0) := Number;
        when others =>  number_B(15 downto 0) := (others=>'0');
        end case;
        cnt := cnt +1;  
    end if;

    Sign_A<=number_A(31);
    Exponent_A<=number_A(30 downto 23);
    Mantissa_A<="1" & number_A(22 downto 0);

    Sign_B<=number_B(31);
    Exponent_B<=number_B(30 downto 23);
    Mantissa_B<="1" & number_B(22 downto 0);

end if;
end process; 

When I ran simulation, I observed that my signals (cnt2 and the others signals) don't change. I tried to declare a variable cnt inside process, but the result is the same.

What am I doing wrong? Do you have any suggestions? Thank you :)

Testbench:

entity test is

    --  Port ( );

    end test;

    architecture Behavioral of test is
    component insert
        Port ( Clk : in STD_LOGIC;
               Enter : in STD_LOGIC;
               Number : in STD_LOGIC_VECTOR (15 downto 0);

               Sign_A : out STD_LOGIC;
               Exponent_A : out STD_LOGIC_VECTOR (7 downto 0);
               Mantissa_A : out STD_LOGIC_VECTOR (23 downto 0);

               Sign_B : out STD_LOGIC;
               Exponent_B : out STD_LOGIC_VECTOR (7 downto 0);
               Mantissa_B : out STD_LOGIC_VECTOR (23 downto 0)
               );
    end component;

    signal Enter :  STD_LOGIC;
    signal  Number :  STD_LOGIC_VECTOR (15 downto 0);          
    signal  Sign_A :  STD_LOGIC;
    signal  Exponent_A :  STD_LOGIC_VECTOR (7 downto 0);
    signal  Mantissa_A :  STD_LOGIC_VECTOR (23 downto 0);          
    signal  Sign_B :  STD_LOGIC;
    signal  Exponent_B :  STD_LOGIC_VECTOR (7 downto 0);
    signal   Mantissa_B :  STD_LOGIC_VECTOR (23 downto 0);
    signal Clk : STD_LOGIC := '0';
    constant CLK_PERIOD : Time := 10 ns;

    begin

    DUT: insert port map
      (
      Clk=>Clk,
      Enter=>Enter,
      Number=>Number,
      Sign_A=>Sign_A,
      Mantissa_A=>Mantissa_A,
      Exponent_A=>Exponent_A,
      Sign_B=>Sign_B,
      Mantissa_B=>Mantissa_B,
      Exponent_B=>Exponent_B);


    gen_clk:process
    begin
        Clk <= '1';
        wait for (CLK_PERIOD/2);
        Clk <= '0';
        wait for (CLK_PERIOD/2);
    end process gen_clk;


    genereare: process
    begin
    Number<="0011111101011001";
    Enter<='1';
    Enter<='0';
    wait for CLK_PERIOD;

    Number<="1001100110011010";
    Enter<='1';
    Enter<='0';
    wait for CLK_PERIOD;

    Number<="0100000100100100";
    Enter<='1';
    Enter<='0';
    wait for CLK_PERIOD;

    Number<="1100110011001101";
    Enter<='1';
    Enter<='0';
    wait for CLK_PERIOD;


    end process;

    end Behavioral;