Why the immediate offset in the riscv's JAL instruction has bit order changed?

Question

The bit field is shown below

I don't see the point the of doing this re-ordering of bit-field.

Is there a special kind of manipulation when RISC-V processor is executing this instruction?

there is some explanations at p12 of the User-level ISA v2.2 "Immediate encoding variants" - see J-type. but it does not answer to your question. May be worth to post your question in the riscv-ISA mailing list. — Pierre G., Jul 06 '18 at 08:43
Does this answer your question? [Why are RISC-V S-B and U-J instruction types encoded in this way?](https://stackoverflow.com/questions/58414772/why-are-risc-v-s-b-and-u-j-instruction-types-encoded-in-this-way) — phuclv, Jan 15 '20 at 14:27

score 2 · Accepted Answer · answered Jul 10 '18 at 18:09

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The purpose of the shuffling is to reduce the number of muxs involved in constructing the full sized operand from the immediates across the different instruction types.

For example, the sign-extend bit (which drives a lot wires) is always the same (inst[31]). You can also see that imm[10] is almost always in the same place too, across I-type, S-type, B-type, and J-type instructions.

answered Jul 10 '18 at 18:09

Chris

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But why is it important that imm[10] be in a fixed place ? – FabienM Nov 18 '18 at 15:33

Why the immediate offset in the riscv's JAL instruction has bit order changed?

1 Answers1