Testbench in verilog produces errors saying real expression is being misused

Question

When I run my testbench, it produces the error

ERROR:HDLCompiler:480 - "/home/ise/FPGA/trapezoid/testbed.v" Line 31: Illegal context for real expression

This is my first project in verilog, so I don't really know what's wrong. I'm trying to set up a simple testbunch like on page 10 of this for my code. The code with the UCF compiles just fine, so it must be something in the testbench. The testbench code is pretty similar to the code in the powerpoint, so I think it comes from my attempt to set local variables to certain values for the test and my not defining a different input. (I need to do this because to really test this it needs to have two inputs for SIGNAL, but I can't do this with the simple testbed described in the powerpoint. So I set the local variables to what they need to be and carry on.) Note that this error still occurs when SIGNAL is defined as equal to 0.

Any help would be appreciated. I am using the Oracle VM Virtualbox ISE.

Code

module trapverilog(
    input CLK,
    input SIGNAL,
     input x,
     input SUM, // OUT is mapped to SUM on board
    output reg OUT
    );

reg[64:0] yregone;
reg[64:0] yregtwo;
reg[64:0] sum;

always @(posedge CLK)
begin
    yregtwo = yregone;
    yregone = SIGNAL;
    if (yregtwo != 0)
    begin
        sum = ((yregone + yregtwo)*x/2) + SUM; //treats x as plain h, change if treated as h/2
        OUT = sum;
    end
end

endmodule

User Config File

NET "CLK" LOC = P126;
NET "SIGNAL" LOC = P35 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; 
NET "x" LOC = P34 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
NET "OUT" LOC = P33 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;

Testbed

module testbed();
    reg CLK, SIGNAL, x, SUM;
    wire OUT;

// instantiate device under test
trapverilog dut(.CLK(CLK), .SIGNAL(SIGNAL), .x(x), .SUM(SUM), .OUT(OUT));

// apply inputs one at a time
initial begin
    x = 1; CLK = 1; SUM = 0; trapverilog.yregone = 1; trapverilog.yregtwo = 2; #10; // apply input, wait
    if (OUT !== 1.5) $display("failed."); // check
end
endmodule

You still haven't fixed the issues I described in [my previous answer regarding this code](https://stackoverflow.com/a/51618421/149341). You've added a width to _some_ of your signals, but not all -- and you seem to be expecting that the 1-bit signal `OUT` can be equal to a non-integer value? — , Jul 31 '18 at 23:41
Also, you're describing a different error in your subject from what appears in the question. — , Jul 31 '18 at 23:45

score 1 · Answer 1 · answered Jul 31 '18 at 23:47

1

The specific error is a result of you comparing OUT to 1.5 towards the end of the testbench. Unlike some programming languages, Verilog is strongly typed and has many types that cannot be synthesized as you appear to be doing based on your UCF.

However, as duskwuff mentioned, there are quite a few problems with the code youve provided and even with the differences between simulation and synthesis. Testbenches are meant for simulation only while constraint files like UCF's for FGPAs are synthesis-related; so there appears to be alot of confusion on some fundamental concepts.

answered Jul 31 '18 at 23:47

Unn

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How can I compare `OUT` to 1.5 then? Can I compare it to an integer? (E.g., if I do `if OUT*2 !== 3`, would that work? And yeah, I understand that I don't have a very good grasp on this and my code is probably crap - this is my first project with verilog. I'm doing my best to fix problems as they are pointed out. – Auden Young Aug 01 '18 at 00:02
Important to note that all the variables in your code are effectively integers now; you want real numbers but at the level of Verilog, that means implementing them yourself; whether thats IEEE 754 floating point numbers, fixed point values, or something else. Verilog itself does have a non-synthesizable type `real`, but since `OUT` comes from your design, you will need to deal with the complexities of real numbers yourself unless you can find a way to avoid them entirely and stick to integers (as many systems do). – Unn Aug 01 '18 at 00:14
I changed how I handled `OUT` to multiplying by two and then checking if (not) equal to 3 and now it gives me an error saying that `Procedural assignment to a non-register OUT is not permitted, left-hand side should be reg/integer/time/genvar` - why might this be? – Auden Young Aug 01 '18 at 00:20
If you are doing `OUT = 2 * OUT; if (OUT !== 3)`, then you cant assign `OUT` in the block since its a `wire`. – Unn Aug 01 '18 at 00:33
But I thought I defined it as a register...I guess I'll just pick a different test case. – Auden Young Aug 01 '18 at 00:39
Switching to a different testcase where `OUT` doesn't need to be redefined produces the same problem. – Auden Young Aug 01 '18 at 00:42
I would suggest moving to SystemVerilog (SV) rather than traditional Verilog (as it has been replaced by SV and most tools now support enough of it). Verilog has a very hard to grasp concept of nets and variables that does very little but add alot of confusion. In SystemVerilog, everything becomes `logic` and it all is much easier to deal with. – Unn Aug 01 '18 at 00:43

Testbench in verilog produces errors saying real expression is being misused

Code

User Config File

Testbed

1 Answers1