Inter & Intra Delay Confusion with Blocking & NBA in Verilog

Question

Here is the code.

module temp();
  bit a;
  bit w_inter_nonblocking, x_inter_blocking, y_intra_blocking, z_intra_nonblocking;

  always @ (a)
  begin 
    $display("@%0t : Blocking x_inter_blocking", $time());
    #7 x_inter_blocking = a;
  end

  always @ (a)
  begin 
    $display("@%0t : Nonblocking w_inter_nonblocking", $time());
    #7 w_inter_nonblocking <= a;
  end

  always @ (a)
  begin 
    $display("@%0t : Nonblocking z_intra_nonblocking", $time());
    z_intra_nonblocking <= #7 a;
  end

  always @ (a)
  begin
    $display("@%0t : Blocking y_intra_blocking", $time());
    y_intra_blocking = #7 a;
  end

  initial
    forever #5 a = $random();

  initial 
    #150 $finish();

  // initial 
  //   #40 disable karan;

  initial 
  begin
    $dumpvars(0, temp);
    $dumpfile("temp.vcd");
  end
endmodule

Here is the corresponding print statements and waveform.

@10 : Nonblocking z_intra_nonblocking
@10 : Blocking x_inter_blocking
@10 : Nonblocking w_inter_nonblocking
@10 : Blocking y_intra_blocking
@40 : Nonblocking z_intra_nonblocking
@40 : Blocking x_inter_blocking
@40 : Nonblocking w_inter_nonblocking
@40 : Blocking y_intra_blocking
@45 : Nonblocking z_intra_nonblocking
@55 : Nonblocking z_intra_nonblocking
@55 : Blocking x_inter_blocking
@55 : Nonblocking w_inter_nonblocking
@55 : Blocking y_intra_blocking
@60 : Nonblocking z_intra_nonblocking
@70 : Nonblocking z_intra_nonblocking
@70 : Blocking x_inter_blocking
@70 : Nonblocking w_inter_nonblocking
@70 : Blocking y_intra_blocking
@75 : Nonblocking z_intra_nonblocking
@80 : Nonblocking z_intra_nonblocking
@80 : Blocking x_inter_blocking
@80 : Nonblocking w_inter_nonblocking
@80 : Blocking y_intra_blocking
@85 : Nonblocking z_intra_nonblocking
@90 : Nonblocking z_intra_nonblocking
@90 : Blocking x_inter_blocking
@90 : Nonblocking w_inter_nonblocking
@90 : Blocking y_intra_blocking
@95 : Nonblocking z_intra_nonblocking
@105 : Nonblocking z_intra_nonblocking
@105 : Blocking x_inter_blocking
@105 : Nonblocking w_inter_nonblocking
@105 : Blocking y_intra_blocking
@110 : Nonblocking z_intra_nonblocking
@115 : Nonblocking z_intra_nonblocking
@115 : Blocking x_inter_blocking
@115 : Nonblocking w_inter_nonblocking
@115 : Blocking y_intra_blocking
@130 : Nonblocking z_intra_nonblocking
@130 : Blocking x_inter_blocking
@130 : Nonblocking w_inter_nonblocking
@130 : Blocking y_intra_blocking
@135 : Nonblocking z_intra_nonblocking
@140 : Nonblocking z_intra_nonblocking
@140 : Blocking x_inter_blocking
@140 : Nonblocking w_inter_nonblocking
@140 : Blocking y_intra_blocking

As you can see that only Intra Delay with Nonblocking Assignments gives delayed output, rest all delays/assignments give different output.

I know the difference between Inter/Intra delays, however it seems that the always blocks are not getting triggered on alternative events (With delay of #7, if any signal change happens with < #7 delay). However Intra Delay with NBA always block gets triggered properly.

Can anyone please help me here?

score 0 · Accepted Answer · answered Feb 10 '19 at 01:09

0

always @(expression) statement does not mean execute the statement eveytime the expression changes. It means wait fo the expression to change, execute the statement, then repeat going back to waiting for the expression to change.

The problem is when the expression changes while in the process of executing the statement, the change is lost. You can only wait for changes that happen after you start waiting.

It's the same issue as this one I answered earlier.

answered Feb 10 '19 at 01:09

dave_59

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Correct. So ideally `always` block should wait only after all the statements inside that, are completed. But then in case of Intra Delay with NBA, why the always block executes on each expression change? Corresponding signal is `z_intra_nonblocking`. Is it related to Verilog Event Regions? – Karan Shah Feb 10 '19 at 01:12
Non-Blocking Assignment means the statement does not block. It executes in 0 time, so the `statement` completes with no delay, The variable update is scheduled for a later time. – dave_59 Feb 10 '19 at 01:16
Isn't same true for `y_intra_blocking` signal. In that signal also, the variable update is scheduled for a later time, but the RHS is evaluated. Is it related to NBA & Active event regions (`y_intra_blocking` LHS is scheduled in active, `z_intra_nonblocking` LHAS scheduled in NBA region)? – Karan Shah Feb 10 '19 at 01:20
No, blocking assignment mean the statement does not complete until the variable gets updated, Intra blocking assignments is a construct left over from before NBA's were introduced into the Verilog language (1990) and should no longer be used. – dave_59 Feb 10 '19 at 01:25
Ok. So in Inter delay, since statements are not evaluated only, the always block does not get completed.In Intra delay with blocking assignment, since update is not done, statement is not completed. In Intra delay with NBA, due to non blocking, even though update is scheduled later, but statement doesn't block. Thanks for the clarification. :) – Karan Shah Feb 10 '19 at 01:57

Inter & Intra Delay Confusion with Blocking & NBA in Verilog

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