Difference between 1 and 1'b1 in Verilog

Question

What is the difference between just giving 1 and giving 1'b1 in verilog code?

Welcome to Stackoverflow. Please refer https://stackoverflow.com/help/how-to-ask and https://stackoverflow.com/help/mcve . Put more details of the issue that you are facing. Include the relevant code snippets you have tried so far. — Nagama Inamdar, Nov 29 '19 at 09:18
@NJInamdar I expect it's been asked many times before, but as it is, it's a good question. — Matthew Taylor, Nov 29 '19 at 10:38
Note that the size of an unsized number or an integer variable is *at least* 32 bits in Plain-Old-Verilog (everything up to V-2005). The statements below that it is exactly 32 bits are incorrect. — EML, Dec 02 '19 at 16:58

Oldfart · Answer 1 · 2019-11-29T09:00:13.223

12

The 1 is 32 bits wide, thus is the equivalent of 32'b00000000_00000000_00000000_00000001

The 1'b1 is one bit wide.

There are several places where you should be aware of the difference in length but the one most likely to catch you out is in concatenations. {}

reg [ 7:0] A;
reg [ 8:0] B;
   assign A = 8'b10100101;
   assign B = {1'b1,A};  // B is 9'b110100101
   assign B = {1,A};     // B is 9'b110100101
   assign B = {A,1'b1};  // B is 9'b101001011
   assign B = {A,1};     // B is 9'b000000001 !!!!

edited Nov 29 '19 at 09:00

answered Nov 29 '19 at 07:53

Oldfart

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Is 32 the default bit length then? – Yashwanth Gopinath Nov 29 '19 at 08:15
@YashwanthGopinath So called _unbased literals_ (eg `1`) in Verilog are 32-bit, signed numbers. It's not a _default_ as such, it's just how it is. – Matthew Taylor Nov 29 '19 at 08:33

score 3 · Answer 2 · answered Nov 29 '19 at 08:20

So, what's the difference between, say,

logic [7:0] count;
...
count <= count + 1'b1;

and

logic [7:0] count;
...
count <= count + 1;

Not a lot. In the first case your simulator/synthesiser will do this:

i) expand the 1'b1 to 8'b1 (because count is 8 bits wide) ii) do all the maths using 8 bits (because now everything is 8 bits wide).

In the second case your simulator/synthesiser will do this:

i) do all the maths using 32 bits (because 1 is 32 bits wide) ii) truncate the 32-bit result to 8 bits wide (because count is 8 bits wide)

The behaviour will be the same. However, that is not always the case. This:

count <= (count * 8'd255) >> 8;

and this:

count <= (count * 255) >> 8;

will behave differently. In the first case, 8 bits will be used for the multiplication (the width of the 8 in the >> 8 is irrelevant) and so the multiplication will overflow; in the second case, 32 bits will be used for the multiplication and so everything will be fine.

I gave this answer because I was reading more into your question than I think you were intending. I see from your comment to another answer that you simply wanted to know how many bits there were in a so called _unbased literal_. Anyway, this answer might be of interest to future Googlers. — Matthew Taylor, Nov 29 '19 at 08:36

score 2 · Answer 3 · answered Nov 29 '19 at 18:01

1'b1 is an binary, unsigned, 1-bit wide integral value. In the original verilog specification, 1 had the same type as integer. It was signed, but its width was unspecified. A tool could choose the width base on its host implementation of the int type.

Since Verilog 2001 and SystemVerilog 2005, the width of integer and int was fixed at 32-bits. However, because of this original unspecified width, and the fact that so many people write 0 or 1 without realizing that it is now 32-bits wide, the standard does not allow you to use an unbased literal inside a concatenation. {A,1} is illegal.

Difference between 1 and 1'b1 in Verilog

3 Answers3