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In Xilinx Vivado, I would like to buffer 8 independent AXI streams through a "AXI Virtual FIFO controller". From what I understand, the 8 streams must first be multiplexed into one stream using a "AXI4-Stream switch", and then demultiplexed using a second "AXI4-Stream switch".

The demultiplexing switch "axis_switch_0" uses the "tdest" signal to determine which Mxx_AXIS interface to send each transfer to. The "tdest" signal passes through the "AXI Virtual FIFO controller".

But I cannot figure out how to make the multiplexing switch "axis_switch_1" produce the "tdest" signal based on which Sxx_AXIS interface each transfer came from.

Any ideas?

AXI stream infrastructure

EDIT

This is what happens if I enable TDEST or TUSER in "AXI4-Stream switch". No idea how 3bit TDEST/TUSER on the master interface becomes 24bits on the slave interfaces. TDEST and TUSER misbehaviour in AXI switch

Timmy Brolin
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  • Yes, I have read the PG085 specification. It does not say how to make the N:1 configuration of the switch produce a tdest signal indicating the source stream. It only shows how to make the 1:N configuration use the tdest input to select output stream. – Timmy Brolin Jan 31 '20 at 08:46

3 Answers3

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Reading reports from people trying and failing to do similar things, it eventuelly became clear that the "AXI Virtual FIFO controller" and "AXI4-Stream switch" simply are incapable of multiplexing and buffer streams. No clue what their actual intended purpose is. But they can't do this. Believe it or not.

Ended up implementing it all in HDL.

Timmy Brolin
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Try enabling the TUSER signal and hard-coding the slave side to 0-7 to indicate which slave the data came from.

TUSER param

Justin N
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  • And override the AXI stream connection, and manually wire tuser to tdest? I suppose that could work. Seems strange having to resort to a hack like that in order to make the "AXI Virtual FIFO Controller" work at all. – Timmy Brolin Feb 05 '20 at 11:20
  • Yes, it'd have to be manually wired up. Xilinx does a lot of strange stuff, but I agree that there's not a straightforward way to do this. – Justin N Feb 06 '20 at 00:14
  • I also saw the ability to manually enable TDEST. Not sure if that will just pass through transparently though. But you could try that, and maybe it would save you from manually wiring TUSER->TDEST. – Justin N Feb 06 '20 at 00:15
  • I have edited to OP with a screenshot showing TUSER/TDEST behaviour in the AXI4-Stream switch. No idea how 3 bits on the master interface becomes 24 bits on the slave interfaces. Your suggestions would work if they were transparently forwarded, but I have no idea how this 24 <-> 3 bit translation works. – Timmy Brolin Feb 06 '20 at 09:32
  • I think it's 3 bits per byte, so since you're going from 8 down to 1 byte, there are 3*8 bits in and 3 bits out. So you'd need to replicate the port number 8 times to fill up the 24 bits of input. – Justin N Feb 06 '20 at 11:06
  • Speaking of which, your FIFO is 4 bytes, which doesn't match the mux/demux. Maybe running validate will clean that up. – Justin N Feb 06 '20 at 11:11
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In the input to the mux, the 24 bits for TDEST are treated similar to the data or any of the other signals. Bits 2:0 should be connected to the TDEST[2:0] from/for S00 input, bits 5:3 should be connected to the TDEST[2:0] from S01 input, bits 8:6 ... bits 23:21 for S07. 8 channels * 3 bits/channel = 24 bits. Data is the same. Whatever you put in TDEST on S00 will show up at the other end on you demux and split it to whatever output you have for that address.

If you want data sent on axis_switch_0 port S03 to come out port M03 of axis_switch_1, and your addressing in axis_switch_1 is set up so TDEST=011 routes data to M03, then set bits TDEST[11:9]=3'b011 on axis_switch0 when sending that packet.

ninaleechie
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