Can't get output value for Verilog Test bench (Simulating C17 Circuit from ISCAS 85)

Question

I have attached my code for my design source and test bench. I can't get outputs for N22 and N23.

The first part is the downloaded netlist for C17

module c17 (N1,N2,N3,N6,N7,N22,N23);

input N1,N2,N3,N6,N7;

output N22,N23;

wire N10,N11,N16,N19;

nand NAND2_1 (N10, N1, N3);
nand NAND2_2 (N11, N3, N6);
nand NAND2_3 (N16, N2, N11);
nand NAND2_4 (N19, N11, N7);
nand NAND2_5 (N22, N10, N16);
nand NAND2_6 (N23, N16, N19);

endmodule

The next part is my testbench that steps through all of the binary inputs, but I can't get outputs.

`timescale 10ns / 1ps

module test;
    reg N1,N2,N3,N6,N7;
    wire N22,N23;
    integer i;


initial begin
$monitor(N1,N2,N3,N6,N7,N22,N23);
for (i=0; i<31; i=i+1)begin
{N1,N2,N3,N6,N7} = i;
#1;
end
end
endmodule

toolic · Answer 1 · 2020-04-16T22:22:43.790

Since wires N22 and N23 are not driven in the testbench, they are always z. You need to add an instance of your c17 module to the testbench:

module test;
    reg N1,N2,N3,N6,N7;
    wire N22,N23;
    integer i;

c17 dut (
        // Inputs:
    .N1   (N1),
    .N2   (N2),
    .N3   (N3),
    .N6   (N6),
    .N7   (N7),
        // Outputs:
    .N22  (N22),
    .N23  (N23)
);

initial begin
    $monitor(N1,N2,N3,N6,N7,N22,N23);
    for (i=0; i<31; i=i+1) begin
        {N1,N2,N3,N6,N7} = i;
        #1;
    end
end
endmodule

Now they toggle between 0 and 1.

Can't get output value for Verilog Test bench (Simulating C17 Circuit from ISCAS 85)

1 Answers1