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I have the following SystemVerilog variable:

bit [5:0] my_bits = 6'h3E;            // my_bits == 6'd62

I want to take the bit-wise inverse of it and then get that result into an int variable, treating the underlying bits as unsigned, so first I did this:

bit [5:0] my_bits_inv = ~my_bits;     // my_bits_inv = 6'b00_0001
int       my_int = int'(my_bits_inv); // my_int = 1

That gave me what I wanted. However, if I combine the inversion and casting into a single step, I get -63:

int       my_int2 = int'(~my_bits); // my_int2 = -63 ???

Presumably it is treating my_bits as 32 bits, then taking the inverse of that to give int'(~32'h0000_003E) = int'(32'hFFFF_FFC1) = -63.

Can someone explain why this happens? Does it have to do with self-determination rules?

toolic
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Evan Cox
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  • The explicit `int'()` cast is unnecessary since the assignment to an `int` variable creates an implicit cast to `int`. Also realize you are taking a chance with these variable declaration initializations as the order they are performed is undefined. But that has no effect on the answer given. – dave_59 Jun 22 '20 at 20:18
  • Thanks Dave for the note of caution. In general I try to be explicit with the casts just for the sake of clarity, and in my real application these were automatic variables in an always block, so ordering should be well defined. However, you're saying that static variable initialization outside of a procedural context is not ordered? So it's impossible to reliably initialize static variables in a module that depend on the initial values of other static variables in the module? – Evan Cox Jun 22 '20 at 20:37
  • https://stackoverflow.com/questions/29822181/prevent-static-initialization-order-fiasco-c – dave_59 Jun 22 '20 at 20:43
  • Isn't that referring to a situation with static variables across multiple classes? I'm not aware of ordering issues happening within a single C comp unit or C++ class, or equivalently within a single module in SV. I mean we've had this figured out with parameters and localparams for a while, why would there be a regression here? – Evan Cox Jun 22 '20 at 20:54
  • There's no difference in the issue of initializing static variables in classes or modules. (Except that with a static class variable the issue more likely results in a fatal null handle reference) The specifc issue I'm brining up is with the dependency on the _initialization_ of one static variable using the _initialization_ of another static variable. It's not with the use of static variables within procedural code. – dave_59 Jun 22 '20 at 21:06
  • Right, we are talking about the same thing I think. Specifically I'm wondering about initializing two static variables within a single module, like so: `module top; int a = 5; int b = a+1; endmodule`. In this case you're saying the value of b is sometimes undefined? – Evan Cox Jun 22 '20 at 21:20
  • Correct according to the LRM. Probably need to ask as a new question since we are off-topic for this question – dave_59 Jun 22 '20 at 21:22

1 Answers1

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Your diagnosis is correct. This is explained in IEEE Std 1800-2017, section 11.6.1 Rules for expression bit lengths. In your case, casting with int' expands my_bits to match the width of int (32) before the bitwise inversion.

Consider also:

$displayb(~my_bits);
$displayb(int'(~my_bits));

Outputs:

000001
11111111111111111111111111000001
toolic
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