RISC-V instruction to write dirty cache line to next level of cache

Question

Are there any RISC-V instructions to write-back dirty cache line to next level of cache, or to main memory, like clwb in x86 or cvac in ARMv8-A?

I want to ensure commit to non-volatile persistent memory.

My intention is to adapt ARMv8_A code mentioned below for RISC-V and execute it in Gem5.

#code

#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <unistd.h>
#include <stdint.h>

void clean_invalidate(uint64_t addr){
        uint64_t ctr_el0 = 0;
        if(ctr_el0 == 0)
                asm volatile("mrs %0, ctr_el0":"=r"(ctr_el0)::);
        const size_t dcache_line_size = 4 << ((ctr_el0 >>16)&15);
        addr = addr & ~(dcache_line_size - 1);
        asm volatile("dc cvau, %0"::"r"(addr):);
}


int main(){
        int a[1000];
        int index = 0;
        uint64_t addr = 0;
        double time_spend = 0.0;
        clock_t begin = clock();
        for(int i=0;i<100;i++){
                index = rand()%1000;
                a[index] = index;
                addr = (uint64_t)(&a[index]);
                asm volatile("dsb ish");
                clean_invalidate(addr);
                asm volatile("dsb ish");
                int b = a[index];
        }
        clock_t end = clock();
        time_spend = (double)(end-begin)/CLOCKS_PER_SEC;
        printf("Time:%f\n",time_spend);
        return 0;
}

Are you looking for a performance hint like x86 [`cldemote`](https://www.felixcloutier.com/x86/cldemote) (only on Tremont atom) that can help other cores load the line sooner, or a guaranteed behaviour suitable for commit to non-volatile memory like x86 [`clwb`](https://www.felixcloutier.com/x86/clwb)? — Peter Cordes, Jul 23 '20 at 11:10
@PeterCordes Thanks for your comment, I am looking for commit to non-volatile memory like x86 clwb. I came across this talk, (https://www.youtube.com/watch?v=HsxoXMdo4L0&t=28s) where the speaker mentioned about including "clwb" to risc-v, but could not find any in latest risc-v ISA specification as well. Thanks once again — Arun Kp, Jul 25 '20 at 15:17
I don't know the answer to your question, but hopefully that clarifies it for future readers. You might want to remove the bit about just pushing out to the next level of cache, because that presumably won't be sufficient to ensure commit to persistent memory. BTW, that inline-asm is buggy: `asm volatile("dsb ish");` does *not* imply a `"memory"` clobber, so it's not ordered (for compile-time reordering) wrt. memory accesses by compiler-generated code. — Peter Cordes, Jul 25 '20 at 15:40

score 4 · Accepted Answer · answered Jul 30 '20 at 17:46

No, the latest version of RISC-V doesn't support data cache line flushing instructions (or even uncacheable writes).

In the presentation you linked to in the comments, the person is only proposing necessary changes to RISC-V to support persistent memory. That person is not affiliated with the RISC-V organization. Officially, there is no indication that any such instructions will be added soon to the ISA.

What you can do is implement clwb (and probably sfence too) yourself in the gem5 simulator, or switch to an ISA that already supports persistent memory.

RISC-V instruction to write dirty cache line to next level of cache

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