Verilog multiplexer

Question

Help me to solve this problem, for following question

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

Solution:

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output [15:0] out );
always@(*) begin
    case(sel)
        0:
            out = a;
        1:
            out = b;
        2:
            out = c;
        3:
            out = d;
        4:
            out = e;
        5:
            out = f;
        6:
            out = g;
        7:
            out = h;
        8:
            out = i;
          
        default:
            out = 1;
       
    endcase
end

endmodule

I don't know what wrong in this code. may be the whole thing.

Note : https://hdlbits.01xz.net/wiki/Mux9to1v

"All bits to 1" is not the same as the output value (which is 16-bits wide) being integer 1. See [this](https://stackoverflow.com/a/19105777/1424875) for guidance. — nanofarad, May 20 '21 at 15:28

score 1 · Accepted Answer · answered May 20 '21 at 18:48

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output reg [15:0] out
);
always @(*) begin
    case(sel)
        0: out = a;
        1: out = b;
        2: out = c;
        3: out = d;
        4: out = e;
        5: out = f;
        6: out = g;
        7: out = h;
        8: out = i;
        default: out = {16{1'b1}}; //..'1 is not the same in every compiler
    endcase
end
endmodule

score 0 · Answer 2 · answered May 20 '21 at 16:52

You don't have endomdule keyword (unexpected end of file).
Always block require reg (procedural assignment to a non-register out). No matter if it is a synchronous or asynchronous always block.

module top_module( 
    input [15:0] a,b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output reg [15:0] out
);

    always @(*) begin
        case(sel)
            0: out = a;
            1: out = b;
            2: out = c;
            3: out = d;
            4: out = e;
            5: out = f;
            6: out = g;
            7: out = h;
            8: out = i;
            default: out = 1;
        endcase
    end

endmodule

score 0 · Answer 3 · answered May 20 '21 at 17:26

Thanks anyway. found a answer. have to fill all outputs bits to 1 with '1.

module top_module( 
input [15:0] a,b, c, d, e, f, g, h, i,
input [3:0] sel,
output reg [15:0] out
);
always @(*) begin
    case(sel)
        0: out = a;
        1: out = b;
        2: out = c;
        3: out = d;
        4: out = e;
        5: out = f;
        6: out = g;
        7: out = h;
        8: out = i;
        default: out = '1;
    endcase
end

endmodule

Verilog multiplexer

3 Answers3