SystemVerilog introduces logic, but why?

Question

Is there any area in SystemVerilog where I can use logic but not reg?

I looked a lot for an answer to this question, but there isn't one.

Answer 1

According to the IEEE Std 1800-2017, section 6.11.2 2-state (two-value) and 4-state (four-value) data types:

The keyword reg does not always accurately describe user intent, as it could be perceived to imply a hardware register. The keyword logic is a more descriptive term. logic and reg denote the same type.

Since they denote the same type, they should be interchangeable.